Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013 / 09 Vol. 21; Iss. 9

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic

Absel, Kalarikkal, Manuel, Lijo, Kavitha, R. K.
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Volume:
21
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2012.2213280
Date:
September, 2013
File:
PDF, 2.31 MB
english, 2013
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