LASIC: Loop-Aware Sleepy Instruction Caches Based on...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014 / 5 Vol. 22; Iss. 5

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

Junwhan Ahn,, Kiyoung Choi,
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Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2013.2265278
Date:
May, 2014
File:
PDF, 558 KB
english, 2014
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