On-Chip Memory Hierarchy in One Coarse-Grained...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014 / 5 Vol. 22; Iss. 5

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

Yansheng Wang,, Leibo Liu,, Shouyi Yin,, Min Zhu,, Peng Cao,, Jun Yang,, Shaojun Wei,
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Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2013.2263155
Date:
May, 2014
File:
PDF, 1.53 MB
english, 2014
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