Analytical Gate Capacitance Modeling of III–V Nanowire...

IEEE Transactions on Electron Devices 2013 / 05 Vol. 60; Iss. 5

Analytical Gate Capacitance Modeling of III–V Nanowire Transistors

Marin, Enrique G., Ruiz, Francisco J. Garcia, Tienda-Luna, Isabel Maria, Godoy, Andres, Gamiz, Francisco
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Volume:
60
Language:
english
Journal:
IEEE Transactions on Electron Devices
DOI:
10.1109/TED.2013.2250288
Date:
May, 2013
File:
PDF, 929 KB
english, 2013
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