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[IEEE Symposium on VLSI Technology - Kyoto, Japan (1997.06.12-1997.06.12)] Symposium on VLSI Technology - A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs

Takao,, Sambonsugi,, Watanabe,, Takatsuka,, Karasawa,, Kawamura,, Hashimoto,, Takagi,, Inoue,, Shimizu,, Yamazaki,, Goto,, Sugii,, Miyajima,, Watanabe,, Aoyama,
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Year:
1997
Language:
english
DOI:
10.1109/VLSIT.1997.623670
File:
PDF, 202 KB
english, 1997
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