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1

Image segmentation and contour detection using fractal coding

Ida, T., Sambonsugi, Y.

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

1998

Language:

english

File:

PDF, 778 KB

english, 1998

2

[IEEE 2009 IEEE International Electron Devices Meeting (IEDM) - Baltimore, MD, USA (2009.12.7-2009.12.9)] 2009 IEEE International Electron Devices Meeting (IEDM) - A study on millisecond annealing (MSA) induced layout dependence for flash lamp annealing (FLA) and laser spike annealing (LSA) in multiple MSA scheme with 45 nm high-performance technology

Miyashita, T., Kubo, T., Kim, Y. S., Nishikawa, M., Tamura, Y., Mitani, J., Okuno, M., Tanaka, T., Suzuki, H., Sakata, T., Kodama, T., Itakura, T., Idani, N., Mori, T., Sambonsugi, Y., Shimizu, A., Ku

Year:

2009

Language:

english

File:

PDF, 615 KB

english, 2009

3

[IEEE 1998 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, USA (9-11 June 1998)] 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) - A perfect process compatible 2.49 μm/sup 2/ embedded SRAM cell technology for 0.13 μm-generation CMOS logic LSIs

Sambonsugi, Y., Maruyama, T., Yano, K., Sakaue, H., Yamamoto, H., Kawamura, E., Ohkubo, S., Tamura, Y., Sugii, T.

Year:

1998

Language:

english

File:

PDF, 405 KB

english, 1998

4

Boundary fitting of extracted objects using LIFS

Takashi Ida, Yoko Sambonsugi, Toshiaki Watanabe

Journal:

Systems and Computers in Japan

Year:

2000

Language:

english

File:

PDF, 1.12 MB

english, 2000

5

Self-affine mapping system and its application to object contour extraction

T. Ida, Y. Sambonsugi

Journal:

IEEE Transactions on Image Processing

Year:

2000

Language:

english

File:

PDF, 362 KB

english, 2000

6

[IEEE Symposium on VLSI Technology - Kyoto, Japan (1997.06.12-1997.06.12)] Symposium on VLSI Technology - A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs

Takao,, Sambonsugi,, Watanabe,, Takatsuka,, Karasawa,, Kawamura,, Hashimoto,, Takagi,, Inoue,, Shimizu,, Yamazaki,, Goto,, Sugii,, Miyajima,, Watanabe,, Aoyama,

Year:

1997

Language:

english

File:

PDF, 202 KB

english, 1997

7

[IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)] 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. - A 320ps access, 3GHz cycle, 144Kb SRAM macro in 90nm CMOS technology using an all-stage reset control signal generator

Akiyoshi, H., Shimizu, H., Matsumoto, T., Kobayashi, K., Sambonsugi, Y.

Year:

2003

Language:

english

File:

PDF, 556 KB

english, 2003

8

[IEEE 2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, USA (11-13 June 2002)] 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) - A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

Nakai, S., Takao, Y., Otsuka, S., Sugiyama, K., Ohta, H., Yamanoue, A., Iriyama, Y., Nanjyo, R., Sekino, S., Nagai, H., Naitoh, K., Nakamura, R., Sambonsugi, Y., Tagawa, Y., Horiguchi, N., Yamamoto, T

Year:

2002

Language:

english

File:

PDF, 375 KB

english, 2002

9

[Japan Soc. Appl. Phys 1999 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (14-16 June 1999)] 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) - Realization of 0.1 μm buried-channel PMOSFETs by device restructuring using tilted well implantation technology

Tanaka, T., Momiyama, Y., Goto, K., Sambonsugi, Y., Deura, M., Sugii, T.

Year:

1999

Language:

english

File:

PDF, 160 KB

english, 1999

10

[Japan Soc. Appl. Phys 1999 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (14-16 June 1999)] 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) - Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs

Goto, K.-I., Sambonsugi, Y., Sugii, T.

Year:

1999

Language:

english

File:

PDF, 183 KB

english, 1999

11

[IEEE 2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, USA (11-13 June 2002)] 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) - 0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

Takao, Y., Nakai, S., Tagawa, Y., Otsuka, S., Sambonsugi, Y., Sugiyama, K., Oota, H., Iriyama, Y., Nanjyo, R., Nagai, H., Naitoh, K., Nakamura, R., Sekino, S., Yamanoue, A., Horiguchi, N., Yamamoto, T

Year:

2002

Language:

english

File:

PDF, 253 KB

english, 2002

12

Image segmentation using fractal coding

Ida, T., Sambonsugi, Y.

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

1995

Language:

english

File:

PDF, 526 KB

english, 1995

13

[IEEE 2007 IEEE International Electron Devices Meeting - Washington, DC, USA (2007.12.10-2007.12.12)] 2007 IEEE International Electron Devices Meeting - High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

Miyashita, T., Ikeda, K., Kim, Y. S., Yamamoto, T., Sambonsugi, Y., Ochimizu, H., Sakoda, T., Okuno, M., Minakata, H., Ohta, H., Hayami, Y., Ookoshi, K., Shimamune, Y., Fukuda, M., Hatada, A., Okabe,

Year:

2007

Language:

english

File:

PDF, 4.77 MB

english, 2007

14

[IEEE International Electron Devices Meeting. Technical Digest. IEDM - San Francisco, CA, USA (10-13 Dec. 2000)] International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - A notched metal gate MOSFET for sub-0.1 μm operation

Pidin, S., Mushiga, M., Shido, H., Yamamoto, T., Sambonsugi, Y., Tamura, Y., Sugii, T.

Year:

2000

Language:

english

File:

PDF, 334 KB

english, 2000

15

[IEEE 1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual - Reno, NV, USA (1998.03.31-1998.04.2)] 1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98 - Hot-carrier degradation mechanism and promising device design of nMOSFETs with nitride sidewall spacer

Sambonsugi, Y., Sugii, T.

Year:

1998

Language:

english

File:

PDF, 425 KB

english, 1998

16

[IEEE 2007 IEEE Symposium on VLSI Technology - Kyoto, Japan (2007.06.12-2007.06.14)] 2007 IEEE Symposium on VLSI Technology - Continuous Scaling Methodology of Planar CMOS Transistors by Suppressing Fluctuation in Carrier Profile

Fukutome, Hidenobu, Yoshida, Eiji, Tajima, Mitsugu, Tanaka, Takuji, Sambonsugi, Yasuhiro, Momiyama, Yoichi

Year:

2007

Language:

english

File:

PDF, 1018 KB

english, 2007

17

Sub-100-nm Device Fabrication using Proximity X-Ray Lithography at Five Levels

Y. Iba, T. Taguchi, F. Kumasaka, T. Iizuka, Y. Sambonsugi, H. Aoyama, K. Deguchi, M. Fukuda, M. Oda, H. Morita, T. Matsuda, K. Horiuchi, Y. Matsui

Year:

2000

Language:

english

File:

PDF, 569 KB

english, 2000

18

[IEEE 6th International Conference on Image Processing (ICIP'99) - Kobe, Japan (24-28 Oct. 1999)] Proceedings 1999 International Conference on Image Processing (Cat. 99CH36348) - Self-affine mapping system for object contour extraction

Ida, T., Sambonsugi, Y.

Year:

1999

Language:

english

File:

PDF, 406 KB

english, 1999

19

Research and development toward KamLAND2-Zen

Nakamura, R., Sambonsugi, H., Shiraishi, K., Wada, Y.

Journal:

Journal of Physics Conference Series

Year:

2020

File:

PDF, 1.10 MB

2020