Inductance model and analysis methodology for high-speed...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002 / 12 Vol. 10; Iss. 6

Inductance model and analysis methodology for high-speed on-chip interconnect

Gala, K., Blaauw, D., Zolotov, V., Vaidya, P.M., Joshi, A.
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Volume:
10
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2002.801619
Date:
December, 2002
File:
PDF, 740 KB
english, 2002
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