Volume 10; Issue 6

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IEEE Transactions on Very Large Scale Integration (VLSI)...
Volume 10; Issue 6

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volume 10; Issue 6

1

Leakage power analysis and reduction during behavioral synthesis

Khouri, K.S., Jha, N.K.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 531 KB

english, 2002

2

Analysis and comparison on full adder block in submicron technology

Alioto, M., Palumbo, G.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 2.32 MB

english, 2002

3

Net-based force-directed macrocell placement for wirelength optimization

Alupoaei, S., Katkoori, S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 611 KB

english, 2002

4

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 565 KB

english, 2002

5

A clock power model to evaluate impact of architectural and technology optimizations

Duarte, D.E., Vijaykrishnan, N., Irwin, M.J.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 1.02 MB

english, 2002

6

Inductive properties of high-performance power distribution grids

Mezhiba, A.V., Friedman, E.G.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 618 KB

english, 2002

7

Inductance model and analysis methodology for high-speed on-chip interconnect

Gala, K., Blaauw, D., Zolotov, V., Vaidya, P.M., Joshi, A.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 740 KB

english, 2002

8

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation

Jai-Ming Lin,, Hsin-Lung Chen,, Yao-Wen Chang,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 1.17 MB

english, 2002

9

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Yu Cao,, Xuejue Huang,, Chang, N.H., Shen Lin,, Nakagawa, O.S., Weize Xie,, Sylvester, D., Chenming Hu,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 530 KB

english, 2002

10

Area-efficient high-speed decoding schemes for turbo decoders

Zhongfeng Wang,, Zhipei Chi,, Parhi, K.K.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 658 KB

english, 2002

11

A methodology for system-level synthesis of mixed-signal applications

Oehler, P., Grimm, C., Waldschmidt, K.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 598 KB

english, 2002

12

ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits

Shanq-Jang Ruan,, Naroska, E., Yen-Jen Chang,, Lai, F., Schwiegelshohn, U.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 626 KB

english, 2002

13

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Kopcsay, G.V., Krauter, B., Widiger, D., Deutsch, A., Rubin, B.J., Smith, H.H.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 724 KB

english, 2002

14

On-chip inductance cons and pros

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 445 KB

english, 2002

15

Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique

Karri, R., Kaijie Wu,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 575 KB

english, 2002

16

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Givargis, T., Vahid, F., Henkel, J.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 456 KB

english, 2002

17

Functional vector generation for sequential HDL models under an observability-based code coverage metric

Fallah, F., Ashar, P., Devadas, S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 376 KB

english, 2002

18

On-chip induction modeling: basics and advanced methods

Beattie, M.W., Pileggi, L.T.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 1.14 MB

english, 2002

19

Managing on-chip inductive effects

Massoud, Y., Majors, S., Kawa, J., Bustami, T., MacMillen, D., White, J.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 1.03 MB

english, 2002

20

Efficient inductance extraction using circuit-aware techniques

Hu, H., Sapatnekar, S.S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2002

Language:

english

File:

PDF, 786 KB

english, 2002

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