Solder joints layout design and reliability enhancements of...

Microelectronics Reliability 2007 Vol. 47; Iss. 2-3

Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

Chang-Chun Lee, Chien-Chen Lee, Hsiao-Tung Ku, Shu-Ming Chang, Kuo-Ning Chiang
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Volume:
47
Year:
2007
Language:
english
Pages:
9
DOI:
10.1016/j.microrel.2006.09.004
File:
PDF, 1.41 MB
english, 2007
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