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Performance improvement of CMOS device utilizing poly-Si/HfSiON gate stack and its reliability concern for 65 nm technology and beyond
N. Kimizuka, Y. Yasuda, T. Abe, S. Fujieda, T. Iwamoto, I. Yamamoto, K. Takano, Y. Akiyama, K. Tsuneki, K. ImaiVolume:
9
Year:
2006
Language:
english
Pages:
10
DOI:
10.1016/j.mssp.2006.10.050
File:
PDF, 716 KB
english, 2006