Seu mitigation for half-latches in xilinx virtex FPGAs

IEEE Transactions on Nuclear Science 2003 / 12 Vol. 50; Iss. 6

Seu mitigation for half-latches in xilinx virtex FPGAs

Graham, P., Caffrey, M., Johnson, D.E., Rollins, N., Wirthlin, M.
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Volume:
50
Language:
english
Journal:
IEEE Transactions on Nuclear Science
DOI:
10.1109/TNS.2003.820744
Date:
December, 2003
File:
PDF, 374 KB
english, 2003
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