Safety property verification using sequential SAT and...

IEEE Design & Test of Computers 2004 / 03 Vol. 21; Iss. 2

Safety property verification using sequential SAT and bounded model checking

Parthasarathy, G., Iyer, M.K., Kwang-Ting Tim Cheng,, Wang, L.-C.
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Volume:
21
Language:
english
Journal:
IEEE Design & Test of Computers
DOI:
10.1109/mdt.2004.1277906
Date:
March, 2004
File:
PDF, 436 KB
english, 2004
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