Effective Method for Simultaneous Gate Sizing and $V$ th...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2014 / 04 Vol. 33; Iss. 4

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation

Flach, Guilherme, Reimann, Tiago, Posser, Gracieli, Johann, Marcelo, Reis, Ricardo
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Volume:
33
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/tcad.2014.2305847
Date:
April, 2014
File:
PDF, 770 KB
english, 2014
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