Josephson 4 K-bit cache memory design for a prototype...

Journal of Applied Physics 1985 Vol. 58; Iss. 6

Josephson 4 K-bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing

Henkels, W. H., Geppert, L. M., Kadlec, J., Epperlein, P. W., Beha, H., Chang, W. H., Jaeckel, H.
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Volume:
58
Year:
1985
Language:
english
Journal:
Journal of Applied Physics
DOI:
10.1063/1.336303
File:
PDF, 1.18 MB
english, 1985
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