Voltage-Aware Chip-Level Design for Reliability-Driven...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2014 / 9 Vol. 33; Iss. 9

Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips

Yeh, Sheng-Han, Chang, Jia-Wen, Huang, Tsung-Wei, Yu, Shang-Tsung, Ho, Tsung-Yi
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Volume:
33
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/tcad.2014.2331340
Date:
September, 2014
File:
PDF, 2.69 MB
english, 2014
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