IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

1

Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods

Li, Yongfu, Zhang, Zhe, Chua, Dingjuan, Lian, Yong

Journal:

Year:

2014

Language:

english

File:

PDF, 4.71 MB

english, 2014

2

Functional Broadside Tests for Multistep Defect Diagnosis

Pomeranz, Irith

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 889 KB

english, 2014

3

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs

Bernardeschi, Cinzia, Cassano, Luca, Domenici, Andrea, Sterpone, Luca

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 1.99 MB

english, 2014

4

Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs

Wang, Ran, Chakrabarty, Krishnendu, Eklow, Bill

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 3.30 MB

english, 2014

5

Compositional Performance Verification of Network-on-Chip Designs

Holcomb, Daniel E., Seshia, Sanjit A.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 1.92 MB

english, 2014

6

Scalable Compact Modeling for On-Chip Passive Elements with Correlated Parameter Extraction and Adaptive Boundary Compression

Yao, Jian, Ye, Zuochang, Wang, Yan

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 1.48 MB

english, 2014

7

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

Shih, Hsiu-Chuan, Luo, Pei-Wen, Yeh, Jen-Chieh, Lin, Shu-Yen, Kwai, Ding-Ming, Lu, Shih-Lien, Schaefer, Andre, Wu, Cheng-Wen

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 3.18 MB

english, 2014

8

Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips

Yeh, Sheng-Han, Chang, Jia-Wen, Huang, Tsung-Wei, Yu, Shang-Tsung, Ho, Tsung-Yi

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 2.69 MB

english, 2014

9

Leveraging Gate-Level Properties to Identify Hardware Timing Channels

Oberg, Jason, Meiklejohn, Sarah, Sherwood, Timothy, Kastner, Ryan

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 1018 KB

english, 2014

10

ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips

Liu, Sean Shih-Ying, Chang, Chung-Hung, Chen, Hung-Ming, Ho, Tsung-Yi

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 3.84 MB

english, 2014

11

Efficient Localization Methods for Passivity Enforcement of Linear Dynamical Models

Mahmood, Zohaib, Grivet-Talocia, Stefano, Chinea, Alessandro, Calafiore, Giuseppe C., Daniel, Luca

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 2.02 MB

english, 2014

12

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

Kim, Dae Hyun, Mukhopadhyay, Saibal, Lim, Sung Kyu

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 3.12 MB

english, 2014

13