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Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement
S. Reggiani, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. WiseVolume:
54
Year:
2010
Language:
english
Pages:
7
DOI:
10.1016/j.sse.2010.04.014
File:
PDF, 1.00 MB
english, 2010