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Selection of gate length and gate bias to make nanoscale metal–oxide-semiconductor transistors less sensitive to both statistical gate length variation and temperature variation
Peizhen Yang, W.S. Lau, Seow Wei Lai, V.L. Lo, S.Y. Siah, L. ChanVolume:
54
Year:
2010
Language:
english
Pages:
8
DOI:
10.1016/j.sse.2010.06.026
File:
PDF, 1.25 MB
english, 2010