A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a...

Integration, the VLSI Journal 2005 Vol. 38; Iss. 3

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan Goda, Russell P. Kraft, John F. McDonald
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Volume:
38
Year:
2005
Language:
english
Pages:
16
DOI:
10.1016/j.vlsi.2004.07.005
File:
PDF, 1.08 MB
english, 2005
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