Volume 38; Issue 3

Integration, the VLSI Journal

Volume 38; Issue 3

1

Automatic cell placement for quantum-dot cellular automata

Ramprasad Ravichandran, Sung Kyu Lim, Mike Niemier

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 208 KB

english, 2005

2

Optimization of the VTcontrol method for low-power ultra-thin double-gate SOI logic circuits

Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khakifirooz, Ali Afzali-Kusha

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 194 KB

english, 2005

3

A 10 GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan Goda, Russell P. Kraft, John F. McDonald

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 1.08 MB

english, 2005

4

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 1.90 MB

english, 2005

5

An efficient architecture for lifting-based two-dimensional discrete wavelet transforms

S. Barua, J.E. Carletta, K.A. Kotteri, A.E. Bell

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 245 KB

english, 2005

6

Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

Phillip Chin, Charles A. Zukowski, George D. Gristede, Stephen V. Kosonocky

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 324 KB

english, 2005

7

Design and optimization of MOS current mode logic for parameter variations

Hassan Hassan, Mohab Anis, Mohamed Elmasry

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 439 KB

english, 2005

8

Complete automatic Q tuning system on a chip

Roghoyeh Salmeh, Brent J. Maundy

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 444 KB

english, 2005

9

Detection probabilities of interconnect breaks: an analysis

Shalini Ghosh, F. Joel Ferguson

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 249 KB

english, 2005

10

High-speed systolic architectures for finite field inversion

Z. Yan, D.V. Sarwate, Z. Liu

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 319 KB

english, 2005

11

Logic-level mapping of high-level faults

F. Fummi, C. Marconcini, G. Pravadelli

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 517 KB

english, 2005

12

Equidistance routing in high-speed VLSI layout design

Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 355 KB

english, 2005

13

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

M. Monchiero, G. Palermo, M. Sami, C. Silvano, V. Zaccaria, R. Zafalon

Journal:

Integration, the VLSI Journal

Year:

2005

Language:

english

File:

PDF, 216 KB

english, 2005