CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 / 7 Vol. 23; Iss. 7

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Jouppi, Norman P., Kahng, Andrew B., Muralimanohar, Naveen, Srinivas, Vaishnav
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Volume:
23
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2014.2334635
Date:
July, 2015
File:
PDF, 3.29 MB
english, 2015
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