IEEE Transactions on Very Large Scale Integration (VLSI) Systems

1

Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms

Neves, Nuno, Sebastiao, Nuno, Matos, David, Tomas, Pedro, Flores, Paulo, Roma, Nuno

Journal:

Year:

2015

Language:

english

File:

PDF, 2.85 MB

english, 2015

2

VLSI Design for SVM-Based Speaker Verification System

Wang, Jia-Ching, Lian, Li-Xun, Lin, Yan-Yu, Zhao, Jia-Hao

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.04 MB

english, 2015

3

An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset

Rabuske, Taimur, Rabuske, Fabio, Fernandes, Jorge, Rodrigues, Cesar

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.23 MB

english, 2015

4

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

Jeong, Hanwool, Kim, Taewon, Song, Taejoong, Kim, Gyuhong, Jung, Seong-Ook

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.30 MB

english, 2015

5

A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology

Kim, Tony Tae-Hyoung, Lu, Pong-Fei, Jenkins, Keith A., Kim, Chris H.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.48 MB

english, 2015

6

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis

Lin, Chia-Chun, Sur-Kolay, Susmita, Jha, Niraj K.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 5.58 MB

english, 2015

7

A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization

Kim, Jintae, Lee, Minjae

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.35 MB

english, 2015

8

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Gines, Antonio Jose, Peralias, Eduardo, Rueda, Adoracion

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.11 MB

english, 2015

9

A High-Performance On-Chip Bus (MSBUS) Design and Verification

Yang, Xiaokun, Andrian, Jean H.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.10 MB

english, 2015

10

An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling

Yao, Jian, Ye, Zuochang, Wang, Yan

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.00 MB

english, 2015

11

Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital Communication

Xiu, Liming

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.97 MB

english, 2015

12

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

Zeng, Xiaoyang, Li, Yi, Zhang, Yuejun, Tan, Shujie, Han, Jun, Zhang, Xingxing, Zhang, Zhang, Cheng, Xu, Han, Jun, Yu, Zhiyi

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.08 MB

english, 2015

13

A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

Oh, Tak-Jun, Hwang, In-Chul

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.59 MB

english, 2015

14

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Marella, Sravan K., Sapatnekar, Sachin S.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.00 MB

english, 2015

15

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

Kundu, Subhadip, Chattopadhyay, Santanu, Sengupta, Indranil, Kapur, Rohit

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.64 MB

english, 2015

16

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong, Na, Wang, Jinhui, Jiang, Shixiong, Sridhar, Ramalingam

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 7.03 MB

english, 2015

17

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

Kao, Mac Y. C., Tsai, Kun-Ting, Chang, Shih-Chieh

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.66 MB

english, 2015

18

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability

Yang, Chi-Heng, Lin, Yi-Min, Chang, Hsie-Chia, Lee, Chen-Yi

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.92 MB

english, 2015

19

On the Efficacy of Through-Silicon-Via Inductors

Tida, Umamaheswara Rao, Yang, Rongbo, Zhuo, Cheng, Shi, Yiyu

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 4.63 MB

english, 2015

20

New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies

Shomalnasab, Gholamreza, Zhang, Lihong

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.28 MB

english, 2015

21

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Jouppi, Norman P., Kahng, Andrew B., Muralimanohar, Naveen, Srinivas, Vaishnav

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.29 MB

english, 2015

23

Corrections to “Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction” [Mar 15 534-543]

Joshi, Rajiv V., Kanj, Rouwaida

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 51 KB

english, 2015

24