Enhancement of gettering efficiencies of different silicon...

Enhancement of gettering efficiencies of different silicon substrates during a 0.18 μm LTB CMOS process simulation –: Stratigraphy by a novel chemical ultra-trace depth-profiling

R. Hoelzl, L. Fabry, K.-J. Range, R. Wahlich, G. Kissinger
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Volume:
56
Year:
2001
Language:
english
Pages:
4
DOI:
10.1016/s0167-9317(00)00519-0
File:
PDF, 150 KB
english, 2001
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