Three-Dimensional Wafer Stacking Using Cu TSV Integrated...

Journal of Low Power Electronics and Applications 2014 / 05 Vol. 4; Iss. 2

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Batra, Pooja, Skordas, Spyridon, LaTulipe, Douglas, Winstel, Kevin, Kothandaraman, Chandrasekharan, Himmel, Ben, Maier, Gary, He, Bishan, Gamage, Deepal, Golz, John, Lin, Wei, Vo, Tuan, Priyadarshini,
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Volume:
4
Language:
english
Journal:
Journal of Low Power Electronics and Applications
DOI:
10.3390/jlpea4020077
Date:
May, 2014
File:
PDF, 1.09 MB
english, 2014
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