A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked...

IEEE Solid-State Circuits Letters 2019 / 10 Vol. 2; Iss. 10

A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability

Truesdell, Daniel S., Dissanayake, Anjana, Calhoun, Benton H.
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Volume:
2
Journal:
IEEE Solid-State Circuits Letters
DOI:
10.1109/lssc.2019.2946767
Date:
October, 2019
File:
PDF, 1.63 MB
2019
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