Volume 2; Issue 10

IEEE Solid-State Circuits Letters

Volume 2; Issue 10

1

A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability

Truesdell, Daniel S., Dissanayake, Anjana, Calhoun, Benton H.

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

Language:

english

File:

PDF, 1.63 MB

english, 2019

2

INFORMATION FOR AUTHORS

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

Language:

english

File:

PDF, 66 KB

english, 2019

3

A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability

Truesdell, Daniel S., Dissanayake, Anjana, Calhoun, Benton H.

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

File:

PDF, 1.63 MB

2019

4

INFORMATION FOR AUTHORS

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

File:

PDF, 66 KB

2019

5

Table of contents

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

Language:

english

File:

PDF, 10.66 MB

english, 2019

6

IEEE SOLID-STATE CIRCUITS LETTERS

Journal:

IEEE Solid-State Circuits Letters

Year:

2019

File:

PDF, 2.74 MB

2019