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Managing annealing pattern effects in 45 nm low power CMOS technology
P. Morin, F. Cacho, R. Beneyton, B. Dumont, A. Colin, H. Bono, A. Villaret, E. Josse, R. BianchiniVolume:
54
Year:
2010
Language:
english
Pages:
6
DOI:
10.1016/j.sse.2010.04.024
File:
PDF, 1.21 MB
english, 2010