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Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs
Yoshino K. Fukai, Kimiyoshi Yamasaki, Kazumi NishimuraVolume:
39
Year:
1999
Language:
english
Pages:
6
DOI:
10.1016/s0026-2714(99)00186-9
File:
PDF, 184 KB
english, 1999