Volume 15; Issue 2

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IEEE Transactions on Semiconductor Manufacturing
Volume 15; Issue 2

IEEE Transactions on Semiconductor Manufacturing

Volume 15; Issue 2

1

On designing sub-70-nm semiconductor materials and processes

Zhirnov, V.V., Cavin, R.K., Herr, D.J.C., Wooldridge, T.A.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 466 KB

english, 2002

2

Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide

Nara, A., Yasuda, N., Satake, H., Toriumi, A.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 247 KB

english, 2002

3

Semiconductor microlenses fabricated by one-step focused ion beam direct writing

. Yongqi Fu, N. Bryan

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 181 KB

english, 2002

4

Manufacturability of single and double-gate ultrathin silicon film fully depleted SOI technologies

Z. Krivokapic, W. Heavlin

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 301 KB

english, 2002

5

High yielding self-aligned contact process for a 0.150-μm DRAM technology

T. Rupp, D. Dobuzinsky, V. Sardesai, Hang-yip Liu, M. Maldei, J. Faltermeier, J. Gambino

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 370 KB

english, 2002

6

Test structures for evaluating strong phase shift lithography

R. Ashton, B. Kane, J. Blatchford, D. Shuttleworth

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 323 KB

english, 2002

7

Lifetime RC time delay of on-chip copper interconnect

Sun, M., Pecht, M.G., Barbe, D.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 322 KB

english, 2002

8

FeRAM retention analysis method based on memory cell read signal voltage measurement

Koike, H., Amanuma, K., Miwa, T., Yamada, J., Toyoshima, H.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 438 KB

english, 2002

9

The double jet ionizer for ULSI manufacturing processes

Imazono, H., Terashige, T., Okano, K.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 233 KB

english, 2002

10

Modeling of dry development in bilayer-resist process for 140-nm contact hole patterning

Sung Bo Hwang,, Kim, W.D., Edgar, T.F.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 310 KB

english, 2002

11

A neural-network approach for semiconductor wafer post-sawing inspection

Chao-Ton Su,, Taho Yang,, Chir-Mour Ke,

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 267 KB

english, 2002

12

On-line learning delivery decision support system for highly product mixed semiconductor foundry

Chih-Yuan Yu,, Han-Pang Huang,

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 269 KB

english, 2002

13

Supply-voltage optimization for below-70-nm technology-node MOSFETs

Wakabayashi, H., Samudra, G.S., Djomehri, I.J., Nayfeh, H., Antoniadis, D.A.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 307 KB

english, 2002

14

Stencil mask ion implantation technology

Shibata, T., Suguro, K., Sugihara, K., Nishihashi, T., Fujiyama, J., Sakurada, Y.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 282 KB

english, 2002

15

Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interconnect

Smith, S., Walton, A.J., Ross, A.W.S., Bodammer, G.K.H., Stevenson, J.T.M.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 325 KB

english, 2002

16

Derivation and implication of a novel DRAM bit cost model

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 244 KB

english, 2002

17

The COB stack DRAM cell at technology node below 100 nm-scaling issues and directions

Kinam Kim,, Moon-Young Jeong,

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 279 KB

english, 2002

18

Understanding a semiconductor process using a full-scale model

Hunter, J., Delp, D., Collins, D., Si, J.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 267 KB

english, 2002

19

Simple cost models of high-process-mix wafer fabs at different capacities

Iwata, Y., Wood, S.C.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 260 KB

english, 2002

20

Metrology technology for the 70-nm node: process control through amplification and averaging microscopic changes

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2002

Language:

english

File:

PDF, 513 KB

english, 2002