IEEE Transactions on Very Large Scale Integration (VLSI) Systems

1

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF $(2^{m})$

Poolakkaparambil, Mahesh, Mathew, Jimson, Jabir, Abusaleh M., Pradhan, Dhiraj K.

Journal:

Year:

2015

Language:

english

File:

PDF, 3.41 MB

english, 2015

2

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors

Han, Jie, Leung, Eugene, Liu, Leibo, Lombardi, Fabrizio

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.12 MB

english, 2015

3

Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits

Gaynor, Brad D., Hassoun, Soha

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.70 MB

english, 2015

4

A Fully Digital ASK Demodulator With Digital Calibration for Bioimplantable Devices

Kafi Kangi, Mohammad, Maymandi-Nejad, Mohammad, Nasserian, Mahshid

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.73 MB

english, 2015

5

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation

Endo, Sho, Li, Yang, Homma, Naofumi, Sakiyama, Kazuo, Ohta, Kazuo, Fujimoto, Daisuke, Nagata, Makoto, Katashita, Toshihiro, Danger, Jean-Luc, Aoki, Takafumi

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 4.84 MB

english, 2015

6

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish, Erfan, Rossi, Davide, Loi, Igor, Benini, Luca

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 6.49 MB

english, 2015

7

Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits

Morrison, Matthew A., Ranganathan, Nagarajan, Ligatti, Jay

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.99 MB

english, 2015

8

Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels

Wang, Zhuo, Lee, Kyong Ho, Verma, Naveen

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 3.23 MB

english, 2015

9

Period Jitter of Frequency-Locked Loops

Joshi, Archit

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.48 MB

english, 2015

10

A Sub- ${\boldsymbol kT}/\boldsymbol q$ Voltage Reference Operating at 150 mV

Albano, Domenico, Crupi, Felice, Cucchi, Francesca, Iannaccone, Giuseppe

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.15 MB

english, 2015

11

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

Shibata, Nobutaro, Gotoh, Yoshinori

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 5.01 MB

english, 2015

12

An $80\times $ Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- $\mu $ m CMOS

Shih, Horng-Yuan, Lin, Sheng-Kai, Liao, Po-Shun

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.19 MB

english, 2015

13

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management

An, Young-Jae, Jung, Dong-Hoon, Ryu, Kyungho, Woo, Seung-Han, Jung, Seong-Ook

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.15 MB

english, 2015

14

A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification

Wang, Qian, Li, Peng, Kim, Yongtae

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 4.14 MB

english, 2015

15

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Lin, James, Mano, Ibuki, Miyahara, Masaya, Matsuzawa, Akira

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 7.15 MB

english, 2015

16

Optimization of Overdrive Signoff in High-Performance and Low-Power ICs

Chan, Tuck-Boon, Kahng, Andrew B., Li, Jiajia, Nath, Siddhartha, Park, Bongil

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.26 MB

english, 2015

17

Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

Han, Taewoo, Choi, Inhyuk, Kang, Sungho

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 2.33 MB

english, 2015

18

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Zhao, Wenfeng, Ha, Yajun, Alioto, Massimo

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 4.26 MB

english, 2015

19

Online Fault Tolerance Technique for TSV-Based 3-D-IC

Zhao, Yi, Khursheed, Saqib, Al-Hashimi, Bashir M.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.59 MB

english, 2015

20

A 1.2-V 450-μW $G_{m}$ - $C$ Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor

Sanchez-Rodriguez, Trinidad, Gomez-Galan, Juan Antonio, Carvajal, Ramon Gonzalez, Sanchez-Raya, Manuel, Munoz, Fernando, Ramirez-Angulo, Jaime

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 1.64 MB

english, 2015

22