Volume 43; Issue 4

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Volume 43; Issue 4

Integration, the VLSI Journal

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

Scaling of analog LDPC decoders in sub-100&#xa0;nm CMOS processes

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Full-chip leakage analysis for 65&#xa0;nm CMOS technology and beyond

Thermal modeling and analysis of 3D multi-processor chips

Scaling of analog LDPC decoders in sub-100 nm CMOS processes

Full-chip leakage analysis for 65 nm CMOS technology and beyond