Volume 58

Integration, the VLSI Journal

Volume 58

1

An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

Sheikh, Ahmad T., El-Maleh, Aiman H.

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 616 KB

english, 2017

2

Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters

Momen, H.G., Yazgi, M., Kopru, R., Saatlo, A.N.

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 927 KB

english, 2017

3

Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs

Mossa, Siraj Fulum, Hasan, Syed Rafay, Elkeelany, Omar

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.55 MB

english, 2017

4

PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol’ indices-based engine

Kourany, Taher, Ghoneima, Maged, Hegazi, Emad, Ismail, Yehea

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.11 MB

english, 2017

5

An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition

Durgesh Nandan,, Kanungo, Jitendra, Mahajan, Anurag

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 732 KB

english, 2017

6

A 0.33V 2.5μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130nm CMOS

Jin, Wei, He, Weifeng, Jiang, Jianfei, Huang, Haichao, Zhao, Xuejun, Sun, Yanan, Chen, Xin, Jing, Naifeng

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.59 MB

english, 2017

7

CMOS Analog Rank Order Filters using positive feedback comparators

Bandala-Hernandez, H.C., Díaz-Sánchez, A., Rocha-Pérez, J.M., Ramírez-Angulo, J., López-Ortega, I.Y., Lemus-López, J., Molinar-Solís, J.E.

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 800 KB

english, 2017

8

A fast temperature-aware fixed-outline floorplanning framework using convex optimization

Khodabandeloo, Behnam, Khonsari, Ahmad, Jasemi, Masoomeh, Taheri, Golnaz

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 858 KB

english, 2017

9

Stitch aware detailed placement for multiple E-beam lithography

Lin, Yibo, Yu, Bei, Zou, Yi, Li, Zhuo, Alpert, Charles J., Pan, David Z.

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.04 MB

english, 2017

10

polynomial basis multipliers for irreducible trinomials

Zhang, Jiajun, Fan, Haining

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 694 KB

english, 2017

11

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Stillmaker, Aaron, Baas, Bevan

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.17 MB

english, 2017

12

A routing framework for technology migration with bump encroachment

Wu, Po-Yi, Mak, Wai-Kei, Wang, Ting-Chi, Zhuo, Cheng, Unda, Kassan, Shi, Yiyu

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.05 MB

english, 2017

13

Cluster-based delta-QMC technique for fast yield analysis

Qui, Nguyen Cao, He, Si-Rong, Liu, Chien-Nan Jimmy

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.26 MB

english, 2017

14

On supporting rapid prototyping of embedded systems with reconfigurable architectures

Koutras, I., Maragos, K., Diamantopoulos, D., Siozios, K., Soudris, D.

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.91 MB

english, 2017

15

Loosely coupled multi-bit flip-flop allocation for power reduction

Moon, Hyoungseok, Kim, Taewhan

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.22 MB

english, 2017

16

A mechanism for detecting on-chip radio frequency interference of field-programmable gate array

Zhong, Hengfei, Huang, Zhuoquan, Chen, Dihu, Su, Tao, Wang, Zixin

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.65 MB

english, 2017

17

A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)

Balcioglu, Yalcin, Dundar, Gunhan

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.82 MB

english, 2017

18

Bio-inspired fault tolerant network on chip

Sethi, Muhammad Athar Javed, Hussin, Fawnizu Azmadi, Hamid, Nor Hisham

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.44 MB

english, 2017

19

Guest editorial – Special issue on hardware assisted techniques for IoT and bigdata applications

Mohanty, Saraju P., Srivastava, Ashok, Hu, Shiyan, Ghosal, Prasun

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 363 KB

english, 2017

20

Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016

Ho, Tsung-Yi, Taskin, Baris

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 171 KB

english, 2017