Volume 37; Issue 5

Journal of Semiconductors

Volume 37; Issue 5
4

A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Year:
2016
Language:
english
File:
PDF, 3.28 MB
english, 2016
6

Performance analysis of charge plasma based dual electrode tunnel FET

Year:
2016
Language:
english
File:
PDF, 2.02 MB
english, 2016
9

Novel trench gate field stop IGBT with trench shorted anode

Year:
2016
Language:
english
File:
PDF, 1.30 MB
english, 2016
15

Researching the silicon direct wafer bonding with interfacial SiO 2 layer

Year:
2016
Language:
english
File:
PDF, 1.68 MB
english, 2016
18

Photoelectric characteristics of CH 3 NH 3 PbI 3 /p-Si heterojunction

Year:
2016
Language:
english
File:
PDF, 2.34 MB
english, 2016
19

An LDMOS with large SOA and low specific on-resistance

Year:
2016
Language:
english
File:
PDF, 667 KB
english, 2016