Volume 41; Issue 11

Microelectronics Reliability

Volume 41; Issue 11

1

Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies

Koen G Verhaege, Christian C Russ

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 747 KB

english, 2001

2

Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-Si phase

K Esmark, W Stadler, M Wendel, H Goßner, X Guggenmos, W Fichtner

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 824 KB

english, 2001

3

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

J Wu, P Juliano, E Rosenbaum

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 197 KB

english, 2001

4

Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits

Yu Wang, Patrick Juliano, Sopan Joshi, Elyse Rosenbaum

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 492 KB

english, 2001

5

The importance of standardizing CDM ESD test head parameters to obtain data correlation

Leo G. Henry, Mark A. Kelly, Tom Diep, Jon Barth

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 707 KB

english, 2001

6

Distributed control based on distributed electronic circuits: application to vibration control

Mahamane Kader, Michel Lenczner, Zeljko Mrcarica

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 3.65 MB

english, 2001

7

Study of the self-alignment of no-flow underfill for micro-BGA assembly

Y.C Chan, P.L Tu, K.C Hung

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 1.16 MB

english, 2001

8

Effects of thermomechanical cycling on lead and lead-free (SnPb and SnAgCu) surface mount solder joints

F.A. Stam, E. Davitt

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 692 KB

english, 2001

9

A method of thermal testing of microsystems

Piotr Bratek, Andrzej Kos

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 1.09 MB

english, 2001

10

Lead-free plastic area array BGAs and polymer stud grid arraysTM package reliability

Dominique Wojciechowski, Moses Chan, Fabrizio Martone

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 837 KB

english, 2001

11

Impact of interface nature on deep sub-micron Al-plug resistance

Bing-Yue Tsui, Tsung-Ju Yang, Tzu-Kun Ku

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 872 KB

english, 2001

12

Tools for contactless testing and simulation of CMOS circuits

F Stellari, F Zappa, S Cova, L Vendrame

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 537 KB

english, 2001

13

On the InGaP/InxGa1−xAs pseudomorphic high electron-mobility transistors for high-temperature operations

Kun-Wei Lin, Kuo-Hui Yu, Wen-Lung Chang, Chih-Kai Wang, Wen-Huei Chiou, Wen-Chau Liu

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 266 KB

english, 2001

14

Effect of SiO2/Si interface roughness on gate current

Ling-Feng Mao, Yao Yang, Jian-Lin Wei, Heqiu Zhang, Ming-Zhen Xu, Chang-Hua Tan

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 286 KB

english, 2001

15

An assessment of the value of added screening of electronic components for commercial aerospace applications

Kendall D Hester, Matthew P Koehler, Hanna Kanciak-Chwialkowski, Brian H Jones

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 123 KB

english, 2001

16

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd

Fuchen Mu, Mingzhen Xu, Changhua Tan, Xiaorong Duan

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 94 KB

english, 2001

17

Foreword – On-Chip ESD

Markus P.J Mergens

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 24 KB

english, 2001

18

Layout and bias options for maximizing Vt1 in cascoded NMOS output buffers

James W. Miller, Michael G. Khazhinsky, James C. Weldon

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 330 KB

english, 2001

19

Influence of device geometry on SOI single-hole transistor characteristics

X Tang, X Baie, J.P Colinge, P Loumaye, C Renaux, V Bayot

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 796 KB

english, 2001

20

Electrical degradation and recovery of dielectrics in n++-poly-Si/SiOx/SiO2/p-sub structures designed for application in low-voltage non-volatile memories

Fernanda Irrera

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 152 KB

english, 2001

21

The development of poled polyimide dielectric layers for simultaneous testing and light guiding applications in MCM-Ds

D.M Mechtel, H.K Charles Jr, A.S Francomacaro

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 299 KB

english, 2001