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51

[IEEE ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design - San Diego, CA, USA (2005.08.8-2005.08.10)] ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. - On-chip digital power supply control for system-on-chip applications

Meijer, M., de Gyvez, J.P., Otten, R.

Year:

2005

Language:

english

File:

PDF, 763 KB

english, 2005

52

[IEEE 1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-96) - Seville, Spain (24-26 June 1996)] 1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications Proceedings (CNNA-96) - Optimal manufacturable CNN array size for time multiplexing schemes

Gunhee Han,, Pineda de Gyvez, J., Sanchez-Sinencio, E.

Year:

1996

Language:

english

File:

PDF, 406 KB

english, 1996

53

[IEEE IEEE International Conference on Test, 2005. - Charlotte, NC, USA (Nov. 8, 2005)] IEEE International Conference on Test, 2005. - Power-scan chain: design for analog testability

Zjajo, A., Henk Jan Bergveld,, Schuttert, R., Pineda de Gyvez, J.

Year:

2005

Language:

english

File:

PDF, 806 KB

english, 2005

54

Mound defect modeling in yield forecasts

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

1994

Language:

english

File:

PDF, 792 KB

english, 1994

55

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

Zjajo, A., de Gyvez, J.P.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2009

Language:

english

File:

PDF, 885 KB

english, 2009

56

[IEEE Comput. Soc. Press ETC 93 Third European Test Conference - Rotterdam, Netherlands (19-22 April 1993)] Proceedings ETC 93 Third European Test Conference - Analog fault diagnosis: a fault clustering approach

Somayajula, S.S., Sanchez-Sinencio, E., Pineda de Gyvez, J.

Year:

1993

Language:

english

File:

PDF, 480 KB

english, 1993

57

[IEEE ISCAS'95 - International Symposium on Circuits and Systems - Seattle, WA, USA (28 April-3 May 1995)] Proceedings of ISCAS'95 - International Symposium on Circuits and Systems - Time-domain analog wavelet transform in real-time

Moreira-Tamayo, O., Pineda de Gyvez, J.

Year:

1995

Language:

english

File:

PDF, 382 KB

english, 1995

58

[IEEE 2011 14th Euromicro Conference on Digital System Design (DSD) - Oulu, Finland (2011.08.31-2011.09.2)] 2011 14th Euromicro Conference on Digital System Design - Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage

Liu, Bo, Pourshaghaghi, Hamid Reza, Londono, Sebastian Moreno, Gyvez, Jose Pineda de

Year:

2011

Language:

english

File:

PDF, 265 KB

english, 2011

59

[IEEE 2010 11th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2010.03.22-2010.03.24)] 2010 11th International Symposium on Quality Electronic Design (ISQED) - Body bias driven design synthesis for optimum performance per area

Meijer, Maurice, de Gyvez, Jose Pineda

Year:

2010

Language:

english

File:

PDF, 271 KB

english, 2010

60

[IEEE International Test Conference 2004 - Charlotte, NC, USA (26-28 Oct. 2004)] 2004 International Conferce on Test - Power supply ramping for quasi-static testing of PLLs

Pineda de Gyvez, J., Gronthoud, G., Cenci, C., Posch, M., Burger, T., Koller, M.

Year:

2004

Language:

english

File:

PDF, 549 KB

english, 2004

61

[IEEE Comput. Soc 8th IEEE European Test Workshop (ETW 03) - Maastricht, Netherlands (25-28 May 2003)] The Eighth IEEE European Test Workshop, 2003. Proceedings. - Process-variability aware delay fault testing of ΔV/sub T/ and weak-open defects

Arumi-Delgado, D., Rodriguez-Montanes, R., de Gyvez, J.P., Gronthoud, G.

Year:

2003

Language:

english

File:

PDF, 314 KB

english, 2003

62

[IEEE 1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-96) - Seville, Spain (24-26 June 1996)] 1996 Fourth IEEE International Workshop on Cellular Neural Networks and their Applications Proceedings (CNNA-96) - Large-image CNN hardware processing using a time multiplexing scheme

Pineda de Gyvez, J., Lei Wang,, Sanchez-Sinencio, E.

Year:

1996

Language:

english

File:

PDF, 409 KB

english, 1996

63

[IEEE Comput. Soc Microelectronic Systems Education Conference - Anaheim, CA, USA (1-2 June 2003)] Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03 - An Analog Integrated Circuit Design Laboratory

Mondragon-Torres, A.F., Mayhugh, T., de Gyvez, J.P., Silva-Martinez, J., Sanchez-Sinencio, E.

Year:

2003

Language:

english

File:

PDF, 208 KB

english, 2003

64

[IEEE 2008 11th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) - Bratislava, Slovakia (2008.04.16-2008.04.18)] 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems - Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm

Zjajo, Amir, Krishnan, Shaji, de Gyvez, Jose Pineda

Year:

2008

Language:

english

File:

PDF, 5.11 MB

english, 2008

65

Time multiplexed color image processing based on a CNN with cell-state outputs

Lei Wang,, De Gyvez, J.P., Sanchez-Sinencio, E.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

1998

Language:

english

File:

PDF, 233 KB

english, 1998

66

[IEEE 2013 NORCHIP - Vilnius, Lithuania (2013.11.11-2013.11.12)] 2013 NORCHIP - A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers

Huang, Yanxiang, Kapoor, Ajay, Rutten, Robert, de Gyvez, Jose Pineda

Year:

2013

Language:

english

File:

PDF, 5.10 MB

english, 2013

67

[IEEE Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - Rome, Italy (18-21 Dec. 1994)] Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - XCNN: a software package for color image processing

Pineda de Gyvez, J.

Year:

1994

Language:

english

File:

PDF, 409 KB

english, 1994

68

One-dimensional discrete-time CNN with multiplexed template-hardware

Manganaro, G., Pineda de Gyvez, J.

Journal:

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Year:

2000

Language:

english

File:

PDF, 232 KB

english, 2000

69

[IEEE European Test Symposium (ETS'05) - Tallinn, Estonia (22-25 May 2005)] European Test Symposium (ETS'05) - Evaluation of Signature-Based Testing of RF/Analog Circuits

Zjajo, A., Pineda de Gyvez, J.

Year:

2005

Language:

english

File:

PDF, 273 KB

english, 2005

70

[IEEE 2008 Design, Automation and Test in Europe - Munich, Germany (2008.03.10-2008.03.14)] 2008 Design, Automation and Test in Europe - Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters

Zjajo, Amir, de Gyvez, Jose Pineda

Year:

2008

Language:

english

File:

PDF, 3.75 MB

english, 2008

71

[IEEE IEEE 2005 Custom Integrated Circuits Conference, 2005. - San Jose, CA, USA (Sept. 18-21, 2005)] Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005. - Programmable techniques for cell stability test and debug in embedded SRAMs

Pavlov, A., Sachdev, M., Pineda de Gyvez, J., Azimane, M.

Year:

2005

Language:

english

File:

PDF, 703 KB

english, 2005

72

[IEEE Comput. Soc. Press IEEE VLSI Test Symposium - Cherry Hill, NJ, USA (25-28 April 1994)] Proceedings of IEEE VLSI Test Symposium - A power supply ramping and current measurement based technique for analog fault diagnosis

Somayajula, S.S., Sanchez-Sinencio, E., Pineda de Gyvez, J.

Year:

1994

Language:

english

File:

PDF, 439 KB

english, 1994

73

[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - DfT for full accessibility of multi-step analog to digital converters

Zjajo, Amir, de Gyvez, Jose Pineda

Year:

2008

Language:

english

File:

PDF, 2.97 MB

english, 2008

74

[IEEE 2011 International Symposium on Low Power Electronics and Design (ISLPED) - Fukuoka, Japan (2011.08.1-2011.08.3)] IEEE/ACM International Symposium on Low Power Electronics and Design - A 1.2V 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOS

Zjajo, Amir, de Gyvez, Jose Pineda

Year:

2011

Language:

english

File:

PDF, 970 KB

english, 2011

75

[IEEE Comput. Soc 19th IEEE VLSI Test Symposium. VTS 2001 - Marina Del Rey, CA, USA (29 April-3 May 2001)] Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 - Average leakage current estimation of CMOS logic circuits

de Gyvez, J.P., van der Wetering, E.

Year:

2001

Language:

english

File:

PDF, 404 KB

english, 2001

76

[IEEE 2014 15th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2014.03.3-2014.03.5)] Fifteenth International Symposium on Quality Electronic Design - Sub-threshold custom standard cell library validation

Liu, Bo, Ashouei, Maryam, Gemmeke, Tobias, de Gyvez, Jose Pineda

Year:

2014

Language:

english

File:

PDF, 1.08 MB

english, 2014

77

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

Zjajo, Amir, Tang, Qin, Berkelaar, Michel, Pineda de Gyvez, Jose, Di Bucchianico, Alessandro, van der Meijs, Nick

Journal:

IEEE Transactions on Circuits and Systems I: Regular Papers

Year:

2011

Language:

english

File:

PDF, 901 KB

english, 2011

78

[IEEE 1997 IEEE International Conference on Evolutionary Computation (ICEC '97) - Indianapolis, IN, USA (13-16 April 1997)] Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97) - DNA computing based on chaos

Manganaro, G., Pineda de Gyvez, J.

Year:

1997

Language:

english

File:

PDF, 543 KB

english, 1997

79

Prelayout interconnect yield prediction

Christie, P., Jose Pineda de Gyvez,

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2003

Language:

english

File:

PDF, 395 KB

english, 2003

80

[IEEE 22nd IEEE VLSI Test Symposium, 2004. - Napa Valley, CA, USA (25-29 April 2004)] 22nd IEEE VLSI Test Symposium, 2004. Proceedings. - Built-in current sensor for ΔI/sub DDQ/ testing of deep submicron digital CMOS ICs

Vazquez, J.R., Pineda de Gyvez, J.

Year:

2004

Language:

english

File:

PDF, 1.37 MB

english, 2004

81

[IEEE Eleventh IEEE European Test Symposium (ETS'06) - Southampton, UK (21-21 May 2006)] Eleventh IEEE European Test Symposium (ETS'06) - Testing and Diagnosis of Power Switches in SOCs

Goel, S.K., Meijer, M., Pineda de Gyvez, J.

Year:

2006

Language:

english

File:

PDF, 550 KB

english, 2006

82

[IEEE 2010 17th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2010) - Athens, Greece (2010.12.12-2010.12.15)] 2010 17th IEEE International Conference on Electronics, Circuits and Systems - Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling

Reza Pourshaghaghi, Hamid, Pineda de Gyvez, Jose

Year:

2010

Language:

english

File:

PDF, 1.23 MB

english, 2010

83

[IEEE 1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings - London, UK (14-17 April 1998)] 1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359) - 1-D discrete time CNN with multiplexed template hardware

Manganaro, G., Pineda de Gyvez, J.

Year:

1998

Language:

english

File:

PDF, 576 KB

english, 1998

84

[IEEE Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - Rome, Italy (18-21 Dec. 1994)] Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94) - A macromodel fault generator for cellular neural networks

Grimaila, M.R., de Gyvez, J.P.

Year:

1994

Language:

english

File:

PDF, 402 KB

english, 1994

85

[IEEE Comput. Soc . 17th International Conference on VLSI Design - Mumbai, India (5-9 Jan. 2004)] 17th International Conference on VLSI Design. Proceedings. - Low energy switch block for FPGAs

Krishnan, R., de Gyvez, J.P.

Year:

2004

Language:

english

File:

PDF, 470 KB

english, 2004

86

[IEEE Comput. Soc. Press 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Dallas, TX, USA (4-6 Nov. 1992)] Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Modeling of 3-dimensional defects in integrated circuits

de Gyvez, J.P., Dani, S.M.

Year:

1992

Language:

english

File:

PDF, 456 KB

english, 1992

87

A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers

Huang, Yanxiang, Kapoor, Ajay, Rutten, Robert, Pineda de Gyvez, José

Journal:

Microprocessors and Microsystems

Year:

2014

Language:

english

File:

PDF, 2.29 MB

english, 2014

88

[IEEE Conference Publications Design Automation and Test in Europe - Dresden, Germany (2014.03.24-2014.03.28)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 - Standard cell library tuning for variability tolerant designs

Fabrie, Sebastien, Echeverri, Juan Diego, Vertreg, Maarten, Gyvez, Jose Pineda de

Year:

2014

Language:

english

File:

PDF, 12.62 MB

english, 2014

89

[IEEE 2010 10th International Conference on Signal Processing (ICSP 2010) - Beijing, China (2010.10.24-2010.10.28)] IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS - An adaptive digital calibration of multi-step A/D converters

Zjajo, Amir, de Gyvez, Jose Pineda

Year:

2010

Language:

english

File:

PDF, 195 KB

english, 2010

90

[IEEE 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) - Dresden (2012.03.12-2012.03.16)] 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Sliding-Mode Control to Compensate PVT Variations in dual core systems

Pourshaghaghi, H. R., Fatemi, H., Pineda de Gyvez, Jose

Year:

2012

Language:

english

File:

PDF, 289 KB

english, 2012

91

Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking

Pourshaghaghi, Hamid Reza, de Gyvez, Jose Pineda

Journal:

IEEE Transactions on Computers

Year:

2013

Language:

english

File:

PDF, 2.20 MB

english, 2013

92

[IEEE IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (1-3 May 1990)] IEEE International Symposium on Circuits and Systems - IC spot-defect and fault semantics-a unified framework

Pineda de Gyvez, J., Jess, J.A.G.

Year:

1990

Language:

english

File:

PDF, 505 KB

english, 1990

93

[IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 - Behavioral testing of cellular neural networks

Willis, J., de Gyvez, J.P.

Year:

1994

Language:

english

File:

PDF, 466 KB

english, 1994

94

[IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 - Single-layer CNN simulator

Lee, C.-C., de Gyvez, J.P.

Year:

1994

Language:

english

File:

PDF, 339 KB

english, 1994

95

[IEEE 33rd Midwest Symposium on Circuits and Systems - Calgary, Alta., Canada (12-14 Aug. 1990)] Proceedings of the 33rd Midwest Symposium on Circuits and Systems - A spot-defect to fault collapsing technique

Di, C., Pineda de Gyvez, J.

Year:

1991

Language:

english

File:

PDF, 448 KB

english, 1991

96

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Glitch-free Discretely Programmable Clock Generation on chip

Meijer, M., Pessolano, F., Pineda de Gyvez, J.

Year:

2005

Language:

english

File:

PDF, 1.36 MB

english, 2005

97

[IEEE 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) - Yasmine Hammamet, Tunisia (2009.12.13-2009.12.16)] 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) - An energy-aware multiplier based on a Configurable-Reuse of points design methodology

Londono, Sebastian Moreno, de Gyvez, Jose Pineda

Year:

2009

Language:

english

File:

PDF, 264 KB

english, 2009

98

[IEEE 43rd IEEE Midwest Symposium on Circuits and Systems - Lansing, MI, USA (8-11 Aug. 2000)] Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) - A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO

Samuel, A.M., de Gyvez, J.P.

Year:

2000

Language:

english

File:

PDF, 472 KB

english, 2000

99

[IEEE Comput. Soc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Japan (25-27 Oct. 2000)] Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Threshold voltage and power-supply tolerance of CMOS logic design families

Kishor, M., Pineda de Gyvez, J.

Year:

2000

Language:

english

File:

PDF, 505 KB

english, 2000

100

[IEEE IEEE International Conference on Test, 2005. - Charlotte, NC, USA (Nov. 8, 2005)] IEEE International Conference on Test, 2005. - Functional vs. multi-VDD testing of RF circuits

Silva, E., Pineda de Gyvez, J., Gronthoud, G.

Year:

2005

Language:

english

File:

PDF, 573 KB

english, 2005