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1

A 90-MHz 16-Mb system integrated memory with direct interface to CPU

Dosaka, K., Yamazaki, A., Watanabe, N., Abe, H., Ohtani, J., Ogawa, T., Ishihara, K., Kumanoya, M.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1996

Language:

english

File:

PDF, 1.71 MB

english, 1996

2

A 64Kbit MOS dynamic RAM with auto/self refresh functions

Michihiro Yamada, Makoto Taniguchi, Toshifumi Kobayashi, Masaki Kumanoya, Takao Nakano

Journal:

Electronics and Communications in Japan (Part I: Communications))

Year:

1983

Language:

english

File:

PDF, 1.13 MB

english, 1983

3

Circuit design of dynamic MOS RAM with consideration of soft error

Yasuji Nagayama, Masaki Kumanoya, Michihiro Yamada, Tsutomu Yoshihara, Makoto Taniguchi

Journal:

Electronics and Communications in Japan (Part I: Communications))

Year:

1982

Language:

english

File:

PDF, 697 KB

english, 1982

4

Decoupling capacitor of substrate bias voltage on dynamic MOS RAM chip

Makoto Taniguchi, Michihiro Yamada, Masaki Kumanoya, Toshifumi Kobayashi, Takano Nakano

Journal:

Electronics and Communications in Japan (Part I: Communications))

Year:

1982

Language:

english

File:

PDF, 508 KB

english, 1982

5

An optimized design for high-performance megabit DRAMs

Masaki Kumanoya, Katsumi Dosaka, Yashuhiro Konishi, Tsutomu Yoshihara, Hideshi Miyatake, Yuto Ikeda, Isao Furuta

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1989

Language:

english

File:

PDF, 762 KB

english, 1989

6

Advances in DRAM interfaces

Kumanoya, M., Ogawa, T., Inoue, K.

Journal:

Year:

1995

Language:

english

File:

PDF, 567 KB

english, 1995

7

On–chip multibit–test scheme for VLSI memories

Hideto Hidaka, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

1988

Language:

english

File:

PDF, 628 KB

english, 1988

8

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

Dosaka, K., Konishi, Y., Hayano, K., Himukashi, K., Yamazaki, A., Iwamoto, H., Kumanoya, M., Hamano, H., Yoshihara, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1992

Language:

english

File:

PDF, 683 KB

english, 1992

9

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Konishi, Y., Kumanoya, M., Yamasaki, H., Dosaka, K., Yoshihara, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1989

Language:

english

File:

PDF, 701 KB

english, 1989

10

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Konishi, Y., Dosaka, K., Komatsu, T., Inoue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M., Yoshihara, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1990

Language:

english

File:

PDF, 526 KB

english, 1990

11

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface

Nakase, Y., Morooka, Y., Perlman, D.J., Kolor, D.J., Jae-Myoung Choi, Shin, H.J., Yoshimura, T., Watanabe, N., Matsuda, Y., Kumanoya, M., Yamada, M.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1999

Language:

english

File:

PDF, 1.08 MB

english, 1999

12

A reliable 1-Mbit DRAM with a multi-bit-test mode

Kumanoya, M., Fujishima, K., Miyatake, H., Nishimura, Y., Saito, K., Matsukawa, T., Yoshihara, T., Nakano, T.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1985

Language:

english

File:

PDF, 900 KB

english, 1985

13

[IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, USA (11-13 June 1998)] 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215) - A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Yoshimura, T., Nakase, Y., Watanabe, N., Morooka, Y., Matsuda, Y., Kumanoya, M., Hamano, H.

Year:

1998

Language:

english

File:

PDF, 264 KB

english, 1998

14

[IEEE Comput. Soc. Press Records of the 1993 IEEE International Workshop on Memory Testing - San Jose, CA, USA (9-10 Aug. 1993)] Records of the 1993 IEEE International Workshop on Memory Testing - A high-speed boundary search Shmoo plot for ULSI memories

Hamada, M., Kumanoya, M., Ishii, M., Kawagoe, T., Niiro, M.

Year:

1993

Language:

english

File:

PDF, 372 KB

english, 1993

15

[IEEE IEEE Custom Integrated Circuits Conference - CICC '94 - San Diego, CA, USA (1-4 May 1994)] Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94 - A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

Iwamoto, H., Watanabe, N., Yamazaki, A., Sawada, S., Murai, Y., Konishi, Y., Itoh, M., Miyamoto, T., Kumanoya, M.

Year:

1994

Language:

english

File:

PDF, 365 KB

english, 1994

16

[IEEE 1993 Symposium on VLSI Circuits - Kyoto, Japan (1997.06.14-1997.06.14)] Symposium on VLSI Circuits - A concurrent operating CDRAM for low cost multi-media

Yamazaki,, Dosaka,, Ogawa,, Kuroiwa,, Fukuda,, Johnson,, Kumanoya,

Year:

1993

Language:

english

File:

PDF, 188 KB

english, 1993

17

[IEEE 37th IEEE International Conference on Solid-State Circuits - San Francisco, CA, USA (14-16 Feb. 1990)] 37th IEEE International Conference on Solid-State Circuits - A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Konishi, Y., Dosaka, K., Komatsu, T., Ionue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M., Yoshihara, T.

Year:

1990

Language:

english

File:

PDF, 314 KB

english, 1990

18

[Institute of Electrical and Electronics Engineers 1985 IEEE International Solid-State Circuits Conference - New York, NY, USA (February 1985)] 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - A 90ns 1Mb DRAM with multi-bit test mode

Kumanoya, M., Fujishima, K., Tsukamoto, K., Nishimura, Y., Saito, K., Matsukawa, T., Yoshihara, T., Nakano, T.

Year:

1985

Language:

english

File:

PDF, 510 KB

english, 1985

19

[IEEE 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers - San Francisco, CA, USA (1993.02.24-1993.02.26)] 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers - Which DRAM will win the great DRAM sweepstakes?

Slater, M., Farmwald, M., Hannah, M., James, D.V., Karp, J.A., Kumanoya, M., Szarek, J.

Year:

1993

Language:

english

File:

PDF, 229 KB

english, 1993

20

[Japan Soc. Applied Phys 1995 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (8-10 June 1995)] Digest of Technical Papers., Symposium on VLSI Circuits. - A 90 MHz 16 Mbit system integrated memory with direct interface to CPU

Dosaka, K., Yamazaki, A., Watanabe, N., Abe, H., Ogawa, T., Ishihara, K., Kumanoya, M.

Year:

1995

Language:

english

File:

PDF, 258 KB

english, 1995

21

[Int. Test Conference International Test Conference - Washington, DC, USA (2-6 Oct. 1994)] Proceedings., International Test Conference - Testing 256k word×16 bit Cache DRAM (CDRAM)

Konishi, Y., Ogawa, T., Kumanoya, M.

Year:

1994

Language:

english

File:

PDF, 95 KB

english, 1994

22

[IEEE 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC - San Francisco, CA, USA (8-10 Feb. 1996)] 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC - A multimedia 32 b RISC microprocessor with 16 Mb DRAM

Shimizu, T., Korematu, J., Satou, M., Kondo, H., Iwata, S., Sawai, K., Okumura, N., Ishimi, K., Nakamoto, Y., Kumanoya, M., Dosaka, K., Yamazaki, A., Ajioka, Y., Tsubota, H., Nunomura, Y., Urabe, T.,

Year:

1996

Language:

english

File:

PDF, 1.15 MB

english, 1996

23

[IEEE 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC - San Francisco, CA, USA (5-7 Feb. 1998)] 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) - Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

Morooka, Y., Nakase, Y., Choi, J.-M., Shin, H.J., Perlman, D.J., Kolor, D.J., Yoshimura, T., Watanabe, N., Matsuda, Y., Kumanoya, M., Yamada, M.

Year:

1998

Language:

english

File:

PDF, 559 KB

english, 1998

24

[IEEE 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers - San Francisco, CA, USA (19-21 Feb. 1992)] 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers - A 100 MHz 4 Mb cache DRAM with fast copy-back scheme

Dosaka, K., Konishi, Y., Hayano, K., Himukashi, K., Yamazaki, A., Hart, C.A., Kumanoya, M., Hamano, H., Yoshihara, T.

Year:

1992

File:

PDF, 252 KB

1992

25

ChemInform Abstract: Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes.

KAKIUCHI, K., UE, M., KUMANOYA, S., TAKEUCHI, H., TOBE, Y., ODAIRA, Y.

Journal:

Year:

1987

File:

PDF, 115 KB

1987

26

Selective Skeletal Rearrangement of Tricyclo[5.4.0.0 1,5 ]undecanes to Tricyclo[5.3.1.0 1,5 ]- and [5.4.0.0 3,8 ]undecanes

Kakiuchi, Kiyomi, Kumanoya, Shuichi, Kobiro, Kazuya, Tobe, Yoshito, Odaira, Yoshinobu

Journal:

Bulletin of the Chemical Society of Japan

Year:

1990

File:

PDF, 431 KB

1990

27

Reductive Rearrangement with Hydride Transfer of Linearly and Angularly Fused Triquinanes

Kakiuchi, Kiyomi, Ue, Masaki, Kumanoya, Shuichi, Takeuchi, Hideyuki, Tobe, Yoshito, Odaira, Yoshinobu

Journal:

Chemistry Letters

Year:

1986

Language:

english

File:

PDF, 5.86 MB

english, 1986

28

SKELETAL REARRANGEMENTS OF TRICYCLO[6.3.0.0 1,6 ]UNDECAN-5-OLS TO FUNCTIONALIZED TRICYCLO[6.3.0.0 1,5 ]- and [5.3.1.0 1,5 ]UNDECANES

Kakiuchi, Kiyomi, Kumanoya, Shuichi, Ue, Masaki, Tobe, Yoshito, Odaira, Yoshinobu

Journal:

Chemistry Letters

Year:

1985

Language:

english

File:

PDF, 6.05 MB

english, 1985

29

ChemInform Abstract: Skeletal Rearrangement of Tricyclo[6.3.0.0 1,6 ]undecan-5-ols to Functionalized Tricyclo[6.3.0.0 1,5 ]- and -[5.3.1.0 1,5 ]-undecanes.

KAKIUCHI, K., KUMANOYA, S., UE, M., TOBE, Y., ODAIRA, Y.

Journal:

Chemischer Informationsdienst

Year:

1986

File:

PDF, 192 KB

1986