Volume 47; Issue 7

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Solid-State Electronics
Volume 47; Issue 7

Solid-State Electronics

Volume 47; Issue 7

1

Quantum corrections in the simulation of decanano MOSFETs

A. Asenov, A.R. Brown, J.R. Watling

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 184 KB

english, 2003

2

High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology

N Collaert, P Verheyen, K De Meyer, R Loo, M Caymax

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 283 KB

english, 2003

3

Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs

F Dieudonné, S Haendler, J Jomaah, F Balestra

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 344 KB

english, 2003

4

The impact of short channel and quantum effects on the MOS transistor mismatch

R Difrenza, P Llinares, G Ghibaudo

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 121 KB

english, 2003

5

A new model for the current factor mismatch in the MOS transistor

R. Difrenza, P. Llinares, G. Ghibaudo

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 166 KB

english, 2003

6

High frequency n-type MODFETs on ultra-thin virtual SiGe substrates

T Hackbarth, H.-J Herzog, F Rinaldi, T Soares, B Holländer, S Mantl, M Luysberg, P.F.P Fichtner

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 201 KB

english, 2003

7

Ag metallization with high electromigration resistance for ULSI

M Hauder, W Hansch, J Gstöttner, D Schmitt-Landsiedel

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 245 KB

english, 2003

8

Simulation and optimization of EJ-MOSFETs

M. Kittler, R. Granzner, F. Schwierz, W. Henschel, T. Wahlbrink, H. Kurz

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 251 KB

english, 2003

9

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

R.J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Städele, W. Rösner

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 506 KB

english, 2003

10

Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices

D. Munteanu, J.L. Autran

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 303 KB

english, 2003

11

Evaluation of circuit performance of ultra-thin-body SOI CMOS

Christian Pacha, Artur Schmal, Thomas Schulz, Ralf Göttsche, Werner Steinhögl

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 259 KB

english, 2003

12

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

K. Rim, R. Anderson, D. Boyd, F. Cardone, K. Chan, H. Chen, S. Christansen, J. Chu, K. Jenkins, T. Kanarsky, S. Koester, B.H. Lee, K. Lee, V. Mazzeo, A. Mocuta, D. Mocuta, P.M. Mooney, P. Oldiges, J.

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 536 KB

english, 2003

13

Electrical characterization of copper interconnects with end-of-roadmap feature sizes

G Schindler, G Steinlesberger, M Engelhardt, W Steinhögl

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 177 KB

english, 2003

14

Impact of parasitic elements on the performance of digital CMOS circuits with Gigabit feature size

Stefan Schwantes, Ralf Göttsche, Wolfgang Krautschneider

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 131 KB

english, 2003

15

Processing technology for the investigation of sub-50 nm copper damascene interconnects

G Steinlesberger, M Engelhardt, G Schindler, J Kretz, W Steinhögl, E Bertagnolli

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 272 KB

english, 2003

16

Simulation of the Esaki-tunneling FET

Peng-Fei Wang, Thomas Nirschl, Doris Schmitt-Landsiedel, Walter Hansch

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 534 KB

english, 2003

17

Fabrication of Schottky barrier MOSFETs on SOI by a self-assembly CoSi2-patterning method

Qing-Tai Zhao, Patrick Kluth, Stephan Winnerl, Siegfried Mantl

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 154 KB

english, 2003

18

Static and low frequency noise characterization in surface- and buried-mode 0.1 μm PMOSFETS

M. Fadlallah, G. Ghibaudo, J. Jomaah, G. Guégan

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 391 KB

english, 2003

19

Foreword

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 34 KB

english, 2003

20

Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides

F Lime, C Guiducci, R Clerc, G Ghibaudo, C Leroux, T Ernst

Journal:

Solid-State Electronics

Year:

2003

Language:

english

File:

PDF, 232 KB

english, 2003

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