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1

Area-efficient linear regulator with ultra-fast load regulation

Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2005

Language:

english

File:

PDF, 760 KB

english, 2005

2

[IEEE 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (15-19 Feb. 2004)] 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) - 64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

Franca-Neto, L.M., Bishop, R.E., Bloechel, B.A.

Year:

2004

Language:

english

File:

PDF, 538 KB

english, 2004

3

[IEEE ESSCIRC 2004 - 29th European Solid-State Circuits Conference - Estoril, Portugal (16-18 Sept. 2003)] ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) - 17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18μm logic CMOS technology

Franca-Neto, L.M., Bloechel, B.A., Soumyanath, K.

Year:

2003

Language:

english

File:

PDF, 594 KB

english, 2003

4

[Widerkehr and Associates 2004 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (17-19 June 2004)] 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) - An area-efficient, integrated, linear regulator with ultra-fast load regulation

Hazucha, P., Karnik, T., Bloechel, B., Parsons, C., Finan, D., Borkar, S.

Year:

2004

Language:

english

File:

PDF, 328 KB

english, 2004

5

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

Mathew, S.K., Anders, M.A., Bloechel, B., Trang Nguyen,, Krishnamurthy, R.K., Borkar, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2005

Language:

english

File:

PDF, 658 KB

english, 2005

6

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

Hazucha, P., Schrom, G., Jaehong Hahn, Bloechel, B.A., Hack, P., Dermer, G.E., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2005

Language:

english

File:

PDF, 967 KB

english, 2005

7

[IEEE 2004 IEEE 35th Annual Power Electronics Specialists Conference - Aachen, Germany (20-25 June 2004)] 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551) - A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

Schrom, G., Hazucha, P., Hahn, J., Gardner, D.S., Bloechel, B.A., Dermer, G., Narendra, S.G., Karnik, T., De, V.

Year:

2004

Language:

english

File:

PDF, 359 KB

english, 2004

8

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process

Hazucha, P., Karnik, T., Walstra, S., Bloechel, B.A., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G.E., Narendra, S., De, V., Borkar, S.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2004

Language:

english

File:

PDF, 891 KB

english, 2004

9

Accurate on-chip interconnect evaluation: a time-domain technique

Soumyanath, K., Borkar, S., Chunyan Zhou, Bloechel, B.A.

Journal:

IEEE Journal of Solid-State Circuits

Year:

1999

Language:

english

File:

PDF, 407 KB

english, 1999

10

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

Vangal, S., Anders, M.A., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Tschanz, J.W., Ye, Y., Somasekhar, D., Bloechel, B.A., Dermer, G.E.,

Journal:

IEEE Journal of Solid-State Circuits

Year:

2002

Language:

english

File:

PDF, 1.41 MB

english, 2002

11

Forward body bias for microprocessors in 130-nm technology generation and beyond

Narendra, S., Keshavarzi, A., Bloechel, B.A., Borkar, S., De, V.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2003

Language:

english

File:

PDF, 710 KB

english, 2003

12

Dynamic sleep transistor and body bias for active leakage power control of microprocessors

Tschanz, J.W., Narendra, S.G., Ye, Y., Bloechel, B.A., Borkar, S., De, V.

Journal:

IEEE Journal of Solid-State Circuits

Year:

2003

Language:

english

File:

PDF, 1.14 MB

english, 2003

13

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Bork

Journal:

IEEE Journal of Solid-State Circuits

Year:

2003

Language:

english

File:

PDF, 1.66 MB

english, 2003

14

[IEEE CICC Custom Integrated Circuits Conference - San Jose, CA, USA (21-24 Sept. 2003)] Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. - Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

Hazucha, P., Karnik, T., Walstra, S., Bloechel, B., Tschanz, J., Maiz, J., Soumyanath, K., Dermer, G., Narendra, S., De, V., Borkar, S.

Year:

2003

Language:

english

File:

PDF, 279 KB

english, 2003

15

[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation

Hazucha, P., Karnik, T., Maiz, J., Walstra, S., Bloechel, B., Tschanz, J., Dermer, G., Hareland, S., Armstrong, P., Borkar, S.

Year:

2003

Language:

english

File:

PDF, 270 KB

english, 2003

16

[IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)] 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. - Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Tschanz, J., Narendra, S., Yibin Ye,, Bloechel, B., Borkar, S., De, V.

Year:

2003

Language:

english

File:

PDF, 387 KB

english, 2003

17

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (3-7 Feb. 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

Anders, M., Mathew, S., Bloechel, B., Thompson, S., Krishnamurthy, R., Soumyanath, K., Borkar, S.

Year:

2002

Language:

english

File:

PDF, 732 KB

english, 2002

18

[Widerkehr and Associates 2004 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (17-19 June 2004)] 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) - Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

Karnik, T., Tschanz, J., Bloechel, B., Hazucha, P., Armstrong, P., Narendra, S., Keshavarzi, A., Soumyanath, K., Dermer, G., Maiz, J., Borkar, S., De, V.

Year:

2004

Language:

english

File:

PDF, 178 KB

english, 2004

19

[Japan Soc. Appl. Phys 2003 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (12-14 June 2003)] 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) - 10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 μm digital CMOS process

Ravi, A., Banerjee, G., Bishop, R.E., Bloechel, B.A., Carley, L.R., Soumyanath, K.

Year:

2003

Language:

english

File:

PDF, 340 KB

english, 2003

20

[Widerkehr and Associates 2004 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (17-19 June 2004)] 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) - A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

Hazucha, P., Schrom, G., Jae-Hong Hahn,, Bloechel, B., Hack, P., Dermer, G., Narendra, S., Gardner, D., Karnik, T., De, V., Borkar, S.

Year:

2004

Language:

english

File:

PDF, 172 KB

english, 2004

21

[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology

Franca-Neto, L.M., Pardy, P., Ly, M.P., Rangel, R., Suthar, S., Syed, T., Bloechel, B., Lee, S., Burnett, C., Cho, D., Kau, D., Fazio, A., Soumyanath, K.

Year:

2002

Language:

english

File:

PDF, 334 KB

english, 2002

22

[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005. - Kyoto, Japan (June 16-18, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005. - Bitline Leakage Compensation (BLC) and Leakage Reduction (BLR) Techniques for 23GHz On-Chip Cache Arrays in Microprocessors on 90nm Logic Technology

Khellah, M., Yibin Ye,, Somasekhar, D., Casper, D., Bloechel, B., Trang Nguyen,, Dermer, G., Zhang, K., Pandya, G., Farhang, A., Vivek De,

Year:

2005

Language:

english

File:

PDF, 694 KB

english, 2005

23

[IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)] 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. - A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

Alvandpour, A., Krishnamurthy, R.K., Eckerbert, D., Apperson, S., Bloechel, B., Borkar, S.

Year:

2003

Language:

english

File:

PDF, 338 KB

english, 2003

24

[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - Dual supply voltage clocking for 5 GHz 130 nm integer execution core

Krishnamurthy, R.K., Hsu, S., Anders, M., Bloechel, B., Chatterjee, B., Sachdev, M., Borkar, S.

Year:

2002

Language:

english

File:

PDF, 172 KB

english, 2002

25

[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - Forward body bias for microprocessors in 130nm technology generation and beyond

Keshavarzi, A., Narendra, S., Bloechel, B., Borkar, S., De, V.

Year:

2002

Language:

english

File:

PDF, 330 KB

english, 2002

26

[Japan Soc. Appl. Phys 2003 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (12-14 June 2003)] 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) - An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 μm digital CMOS process

Ravi, A., Soumyanath, K., Bishop, R.E., Bloechel, B.A., Carley, L.R.

Year:

2003

Language:

english

File:

PDF, 319 KB

english, 2003

27

[ACM Press the 2001 international symposium - Huntington Beach, California, United States (2001..-..)] Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01 - Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Keshavarzi, A., Ma, S., Narendra, S., Bloechel, B., Mistry, K., Ghani, T., Borkar, S., De, V.

Year:

2001

Language:

english

File:

PDF, 265 KB

english, 2001

28

[Japan Soc. Appl. Phys 2001 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (14-16 June 2001)] 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) - Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 μ

Karnik, T., Bloechel, B., Soumyanath, K., De, V., Borkar, S.

Year:

2001

Language:

english

File:

PDF, 254 KB

english, 2001

29

[IEEE 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (15-19 Feb. 2004)] 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) - Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

Narendra, S., Tschanz, J., Hofsheier, J., Bloechel, B., Vangal, S., Hoskote, Y., Tang, S., Somasekhar, D., Keshavarzi, A., Erraguntla, V., Dermer, G., Borkar, N., Borkar, S., De, V.

Year:

2004

Language:

english

File:

PDF, 560 KB

english, 2004

30

[IEEE 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (15-19 Feb. 2004)] 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) - A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS

Mathew, S., Anders, M., Bloechel, B., Nguyen, T., Krishnamurthy, R., Borkar, S.

Year:

2004

Language:

english

File:

PDF, 349 KB

english, 2004

31

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - San Francisco, CA, USA (Feb 3-7, 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - 1.1V 1GHz communications router with on-chip body bias in 150nm CMOS

Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V., Wilson, H., Vangal, S., Pangal, A., Seligman, E., Nair, R., Keshavarzi, A., Bloechel, B., Dermer, G., Mooney, R., Borkar, N., Borkar, S.,

Year:

2002

Language:

english

File:

PDF, 442 KB

english, 2002

32

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - San Francisco, CA, USA (Feb 3-7, 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - 5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Vangal, S., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Anders, M., Tschanz, J., Ye, Y., Somasekhar, D., Bloechel, B., Dermer, G., Krishnam

Year:

2002

Language:

english

File:

PDF, 401 KB

english, 2002

33

[IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, USA (11-13 June 1998)] 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215) - Accurate on-chip interconnect evaluation: a time domain technique

Soumyanth, K., Borkar, S., Chunyan Zhou,, Bloechel, B.

Year:

1998

Language:

english

File:

PDF, 249 KB

english, 1998

34

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - San Francisco, CA, USA (Feb 3-7, 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - A 6.5GHz 130nm single-ended dynamic ALU and instruction scheduler loop

Anders, M., Mathew, S., Bloechel, B., Thompson, S., Krishnamurthy, R., Soumyanath, K., Borkar, S.

Year:

2002

Language:

english

File:

PDF, 315 KB

english, 2002

35

[IEEE ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. - San Francisco, CA, USA (Feb. 6-10, 2005)] ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. - A 110GOPS/W 16b multiplier and reconfigurable PLA loop in 90nm CMOS

Hsu, S., Mathew, S., Anders, M., Bloechel, B., Krishnamurthy, R., Borkar, S.

Year:

2005

Language:

english

File:

PDF, 395 KB

english, 2005

36

[IEEE 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. - Grenoble, France (Sept. 12-16, 2005)] Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. - A 10Mbit, 15Gbytes/sec bandwidth 1R DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

Somasekhar, D., Shih-Lien Lu,, Bloechel, B., Dermer, G., Lai, K., Borkar, S., Vivek De,

Year:

2005

Language:

english

File:

PDF, 323 KB

english, 2005

37

Transient current off-chip sensor circuit for digital IC production testing

Alorda, B., Bloechel, B., Keshavarzi, A., Segura, J.

Journal:

Electronics Letters

Year:

2002

Language:

english

File:

PDF, 172 KB

english, 2002

38

[ACM ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design - Huntington Beach, CA, USA (6-7 Aug. 2001)] ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) - Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Keshavarzi, A., Ma, S., Narendra, S., Bloechel, B., Mistry, K., Ghani, T., Borkar, S., De, V.

Year:

2001

Language:

english

File:

PDF, 496 KB

english, 2001

39

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (3-7 Feb. 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V., Wilson, H., Vangal, S., Pangal, A., Seligman, E., Nair, R., Keshavarzi, A., Bloechel, B., Dermer, G., Mooney, R., Borkar, N., Borkar, S.,

Year:

2002

Language:

english

File:

PDF, 607 KB

english, 2002

40

[IEEE 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (3-7 Feb. 2002)] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) - A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

Vangal, S., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Anders, M., Tschanz, J., Ye, Y., Somasekhar, D., Bloechel, B., Dermer, G., Krishnam

Year:

2002

Language:

english

File:

PDF, 631 KB

english, 2002

41

[IEEE International Test Conference, 2003. ITC 2003. - Washington, DC, USA (Sept. 30-Oct. 2, 2003)] International Test Conference, 2003. Proceedings. ITC 2003. - Chardin: an off-chip transient current monitor with digital interface for production testing

Alorda, B., Bloechel, B., Keshavarzi, A., Segura, J.

Year:

2003

Language:

english

File:

PDF, 748 KB

english, 2003