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51

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection

Pachito, Jackson, Martins, Celestino V., Jacinto, Bruno, Semiao, Jorge, Vazquez, Julio C., Champac, Victor, Santos, Marcelino B., Teixeira, Isabel C., Teixeira, Joao Paulo

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 575 KB

english, 2012

52

[IEEE Fourth IEEE International Caracas Conference on Devices, Circuits and Systems - Oranjestad, Aruba, Netherlands (17-19 April 2002)] Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) - Dynamic logic styles with improved noise-immunity

Mendoza-Hernandez, F., Linarea, M., Champac, V.H.

Year:

2002

Language:

english

File:

PDF, 453 KB

english, 2002

53

Iddq secondary components in CMOS logic circuits preceded by defective stages affected by analogue type faults

Rubio, A., Figueras, J., Champac, V., Rodriguez, R., Segura, J.

Journal:

Electronics Letters

Year:

1991

Language:

english

File:

PDF, 297 KB

english, 1991

54

[IEEE 2020 IEEE Latin American Test Symposium (LATS) - Maceio, Brazil (2020.3.30-2020.4.2)] 2020 IEEE Latin-American Test Symposium (LATS) - Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells

Perez, Z., Mesalles, Javier, Villacorta, H., Vargas, Fabian, Champac, Victor

Year:

2020

File:

PDF, 371 KB

2020

55

[IEEE European Test Symposium (ETS'05) - Tallinn, Estonia (22-25 May 2005)] European Test Symposium (ETS'05) - Testing of Resistive Opens in CMOS Latches and Flip-Flops

Champac, V.H., Zenteno, A., Garcia, J.L.

Year:

2005

Language:

english

File:

PDF, 244 KB

english, 2005

56

Quiescent current analysis and experimentation of defective CMOS circuits

J. A. Segura, V. H. Champac, R. Rodríguez-Montañés, J. Figueras, J. A. Rubio

Journal:

Journal of Electronic Testing

Year:

1992

Language:

english

File:

PDF, 1.26 MB

english, 1992

57

[IEEE 2010 15th IEEE European Test Symposium (ETS) - Praha, Czech Republic (2010.05.24-2010.05.28)] 2010 15th IEEE European Test Symposium - Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2010

Language:

english

File:

PDF, 405 KB

english, 2010

58

[IEEE 2009 10th Latin American Test Workshop - Rio de Janeiro, Brazil (2009.03.2-2009.03.5)] 2009 10th Latin American Test Workshop - A modern look at the CMOS stuck-open fault

Gomez, Roberto, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 419 KB

english, 2009

59

[IEEE 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems - Cancun, Mexico (15-17 March 2000)] Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) - A symbolic circuit analysis-oriented algorithm for finding a common tree of the current and voltage graphs

Sarmiento-Reyes, L.A., Gonzilez-Castolo, L.O., Champac, V.H.

Year:

2000

Language:

english

File:

PDF, 278 KB

english, 2000

60

Signal X-Y zoning to detect inter-signal delay violations

Zenteno, A., Champac, V.H., Figueras, J.

Journal:

Electronics Letters

Year:

2002

Language:

english

File:

PDF, 101 KB

english, 2002

61

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Message from the LATS2015 Chairs

Champac, Victor, Zorian, Yervant, Bolzani Pohls, Leticia, Agrawal, Vishwani

Year:

2015

Language:

english

File:

PDF, 98 KB

english, 2015

62

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

Gomez, A.F., Lavratti, F., Medeiros, G., Sartori, M., Poehls, L. Bolzani, Champac, V., Vargas, F.

Journal:

Microelectronics Reliability

Year:

2016

Language:

english

File:

PDF, 1.46 MB

english, 2016

63

[IEEE 2012 IEEE 30th VLSI Test Symposium (VTS) - Maui, HI, USA (2012.04.23-2012.04.25)] 2012 IEEE 30th VLSI Test Symposium (VTS) - Small-delay defects detection under process variation using Inter-Path Correlation

Galarza-Medina, Francisco J., Garcia-Gervacio, Jose L., Champac, Victor, Orailoglu, Alex

Year:

2012

Language:

english

File:

PDF, 751 KB

english, 2012

64

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops

Zenteno Ramirez, Antonio, Espinosa, Guillermo, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 684 KB

english, 2007

65

[IEEE 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS) - College Station, TX, USA (2014.8.3-2014.8.6)] 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS) - Analysis of fin height on FinFET SRAM cell hardening

Villacorta, Hector, Segura, Jaume, Bota, Sebastia, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 1.07 MB

english, 2014

66

Bit line sensing strategy for testing for data retention faults in CMOS SRAMs

Champac, V.H., Avendaño, V., Linares, M.

Journal:

Electronics Letters

Year:

2000

Language:

english

File:

PDF, 117 KB

english, 2000

67

[IEEE 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Daejeon, South Korea (2015.10.5-2015.10.7)] 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging

Gomez, Andres, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.04 MB

english, 2015

68

[IEEE 2019 IEEE European Test Symposium (ETS) - Baden-Baden, Germany (2019.5.27-2019.5.31)] 2019 IEEE European Test Symposium (ETS) - B-open: A New Defect in Nanometer Technologies due to SADP Process

Forero, Freddy, Renovell, Michel, Champac, Victor

Year:

2019

Language:

english

File:

PDF, 3.72 MB

english, 2019

69

Guest Editorial

Victor Champac, Ingrid Jansch Porto

Journal:

Journal of Electronic Testing

Year:

2003

Language:

english

File:

PDF, 26 KB

english, 2003

70

[IEEE Comput. Soc. Press 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Venice, Italy (27-29 Oct. 1993)] Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems - Analysis of the floating gate defect in CMOS

Champac, V.H., Rubio, A., Figueras, J.

Year:

1993

Language:

english

File:

PDF, 408 KB

english, 1993

71

[IEEE 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009) - Sesimbra-Lisbon, Portugal (2009.06.24-2009.06.26)] 2009 15th IEEE International On-Line Testing Symposium - Built-in aging monitoring for safety-critical applications

Vazquez, J.C., Champac, V., Ziesemer, A.M., Reis, R., Teixeira, I.C., Santos, M.B., Teixeira, J.P.

Year:

2009

Language:

english

File:

PDF, 667 KB

english, 2009

72

[IEEE 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - Dresden (2010.03.8-2010.03.12)] 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - Programmable aging sensor for automotive safety-critical applications

Vazquez, J C, Champac, V, Teixeira, I C, Santos, M B, Teixeira, J P

Year:

2010

Language:

english

File:

PDF, 385 KB

english, 2010

73

ECS Transactions [AAPM 25th Symposium on Microelectronics Technology and Devices - Sao Paulo, Brazil (September 6 - September 9, 2010)] - Equivalent Rectangular Active Region and SPICE Macro Model for Split-Drain MAGFETs

Santillan-Quiñonez, Gerard F., Murphy, Roberto S., Champac, Victor H., Pavanello, M., Claeys, C., Martino, J.

Year:

2010

Language:

english

File:

PDF, 343 KB

english, 2010

74

[IEEE 2016 IEEE East-West Design & Test Symposium (EWDTS) - Yerevan, Armenia (2016.10.14-2016.10.17)] 2016 IEEE East-West Design & Test Symposium (EWDTS) - Critical path selection under NBTI/PBTI aging for adaptive frequency tuning

Gomez, Andres F., Champac, Victor

Year:

2016

Language:

english

File:

PDF, 301 KB

english, 2016

75

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 ||

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 13.42 MB

english, 2018

76

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

José L. García-Gervacio, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 562 KB

english, 2011

77

Logic testability of defective floating gate CMOS latches

Champac, V.H., Figueras, J., Rubio, A.

Journal:

Electronics Letters

Year:

1992

Language:

english

File:

PDF, 309 KB

english, 1992

78

[IEEE 2015 IEEE 33rd VLSI Test Symposium (VTS) - Napa, CA, USA (2015.4.27-2015.4.29)] 2015 IEEE 33rd VLSI Test Symposium (VTS) - An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging

Gomez, Andres, Poehls, Leticia, Vargas, Fabian, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.18 MB

english, 2015

79

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability

Gomez, Andres, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 596 KB

english, 2015

80

[IEEE Comput. Soc Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) - Rio de Janeiro, Brazil (30 Sept.-3 Oct. 1998)] Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) - A graph-oriented CAD tool for establishing the topological diagnostic conditions of analogue circuits

Sarmiento-Reyes, A., Gutierrez-de Anda, M.A., Champac, V.H.

Year:

1998

Language:

english

File:

PDF, 62 KB

english, 1998

81

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths

Villacorta, Hector, Hawkins, Chuck, Champac, Victor, Segura, Jaume, Gomez, Roberto

Journal:

IEEE Design and Test

Year:

2013

Language:

english

File:

PDF, 952 KB

english, 2013

82

[IEEE Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications - Puerto Vallarta, Mexico (26-28 July 1999)] Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) - Design of domino CMOS cells under delay constraint

Zamudio, A., Champac, V.H., Sarmiento-Reyes, A.

Year:

1999

Language:

english

File:

PDF, 336 KB

english, 1999

83

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 || Mathematical Fundamentals

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 875 KB

english, 2018

84

Guest Editorial

Marcelo Lubaszewski, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2001

Language:

english

File:

PDF, 27 KB

english, 2001

85

[IEEE 2013 14th Latin American Test Workshop - LATW - Cordoba, Argentina (2013.04.3-2013.04.5)] 2013 14th Latin American Test Workshop - LATW - Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Villacorta, Hector, Garcia-Gervacio, Jose, Champac, Victor, Bota, Sebastia, Martinez, Jaime, Segura, Jaume

Year:

2013

Language:

english

File:

PDF, 1.79 MB

english, 2013

86

[IEEE 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009) - Sesimbra-Lisbon, Portugal (2009.06.24-2009.06.26)] 2009 15th IEEE International On-Line Testing Symposium - Detectability analysis of small delays due to resistive opens considering process variations

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2009

Language:

english

File:

PDF, 139 KB

english, 2009

87

[IEEE 2010 11th Latin American Test Workshop - LATW - Punta del Este, Uruguay (2010.03.28-2010.03.31)] 2010 11th Latin American Test Workshop - Reliability analysis of small delay defects in vias located in signal paths

Villacorta, Hector, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2010

Language:

english

File:

PDF, 222 KB

english, 2010

88

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Roberto Gómez, Alejandro Girón, Victor H. Champac

Journal:

Journal of Electronic Testing

Year:

2008

Language:

english

File:

PDF, 315 KB

english, 2008

89

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion

Vazquez, J. C., Champac, V., SemiÃ£o, J., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Journal:

Journal of Electronic Testing

Year:

2013

Language:

english

File:

PDF, 539 KB

english, 2013

90

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Test of interconnection opens considering coupling signals

Gomez, R., Giron, A., Champac, V.

Year:

2005

Language:

english

File:

PDF, 291 KB

english, 2005

91

[IEEE Comput. Soc 18th IEEE VLSI Test Symposium - Montreal, Que., Canada (30 April-4 May 2000)] Proceedings 18th IEEE VLSI Test Symposium - Detectability conditions for interconnection open defects

Champac, V.H., Zenteno, A.

Year:

2000

Language:

english

File:

PDF, 222 KB

english, 2000

92

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

Champac, Victor H., Figueras, Joan

Journal:

Year:

1997

Language:

english

File:

PDF, 2.78 MB

english, 1997

93

[IEEE Comput. Soc. Press 13th IEEE VLSI Test Symposium - Princeton, NJ, USA (30 April-3 May 1995)] Proceedings 13th IEEE VLSI Test Symposium - Testability of floating gate defects in sequential circuits

Champac, V.H., Figueras, J.

Year:

1995

Language:

english

File:

PDF, 579 KB

english, 1995

94

[IEEE 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) - Oxford, United Kingdom (2013.9.23-2013.9.27)] 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS) - FinFET SRAM hardening through design and technology parameters considering process variations

Villacorta, Hector, Champac, Victor, Bota, Sebastia, Segura, Jaume

Year:

2013

Language:

english

File:

PDF, 871 KB

english, 2013

95

[IEEE 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - Foz do Iguacu, Brazil (2010.2.24-2010.2.26)] 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - A Short-channel silicon-based Split-Drain MAGFET measuring from 90 µT

Santillan-Quinonez, Gerard F., Champac, Victor, Murphy, Roberto S.

Year:

2010

File:

PDF, 1.19 MB

2010

96

[IEEE Comput. Soc 16th IEEE VLSI Test Symposium - Monterey, CA, USA (26-30 April 1998)] Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) - I/sub DDQ/ testing of opens in CMOS SRAMs

Champac, V.H., Castillejos, J., Figueras, J.

Year:

1998

Language:

english

File:

PDF, 239 KB

english, 1998

97

Skew violation verification in digital interconnect signals based on signal addition

Champac, Victor, Villacorta, Hector, Hernandez, Nestor, Figueras, Joan

Journal:

IEICE Electronics Express

Year:

2014

Language:

english

File:

PDF, 1.45 MB

english, 2014

98

[IEEE 13th Asian Test Symposium - Kenting, Taiwan (15-17 Nov. 2004)] 13th Asian Test Symposium - Analysis and Attenuation Proposal in Ground Bounce

Zenteno, A., Champac, V.H., Renovell, M., Azais, F.

Year:

2004

Language:

english

File:

PDF, 114 KB

english, 2004

99

[IEEE 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Daejeon, South Korea (2015.10.5-2015.10.7)] 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Circuit performance optimization for local intra-die process variations using a gate selection metric

Champac, Victor, Reyes, Alejandra Nicte-ha, Gomez, Andres F.

Year:

2015

Language:

english

File:

PDF, 1.40 MB

english, 2015

100

[IEEE 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - Foz do Iguacu, Brazil (2010.2.24-2010.2.26)] 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - Delay sensing for parametric variations and defects monitoring in safety-critical applications

Vazquez, J.C., Champac, V., Ziesemer, A.M., Reis, R., Teixeira, I.C., Santos, M.B., Teixeira, J.P.

Year:

2010

Language:

english

File:

PDF, 850 KB

english, 2010

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