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1

[IEEE 2012 IEEE Custom Integrated Circuits Conference - CICC 2012 - San Jose, CA, USA (2012.09.9-2012.09.12)] Proceedings of the IEEE 2012 Custom Integrated Circuits Conference - Design solutions for 3D integration and signal integrity

Cao, Yu, Mudanai, Siva

Year:

2012

Language:

english

File:

PDF, 54 KB

english, 2012

2

[IEEE 2014 IEEE International Reliability Physics Symposium (IRPS) - Waikoloa, HI, USA (2014.6.1-2014.6.5)] 2014 IEEE International Reliability Physics Symposium - Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

Prasad, C., Agostinelli, M., Hicks, J., Ramey, S., Auth, C., Mistry, K., Natarajan, S., Packan, P., Post, I., Bodapati, S., Giles, M., Gupta, S., Mudanai, S., Kuhn, K.

Year:

2014

Language:

english

File:

PDF, 909 KB

english, 2014

3

[IEEE 2020 IEEE International Reliability Physics Symposium (IRPS) - Dallas, TX, USA (2020.4.28-2020.5.30)] 2020 IEEE International Reliability Physics Symposium (IRPS) - Modeling Framework for Transistor Aging Playback in Advanced Technology Nodes

Meric, I., Ramey, S., Novak, S., Gupta, S., Mudanai, S. P., Hicks, J.

Year:

2020

File:

PDF, 308 KB

2020

4

Mechanism of Long-Channel Drain-Induced Barrier Lowering in Halo MOSFETs

Roy, A.S., Mudanai, S.P., Stettler, M.

Journal:

IEEE Transactions on Electron Devices

Year:

2011

Language:

english

File:

PDF, 187 KB

english, 2011

5

[IEEE IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - San Francisco, CA, USA (Dec. 13-15, 2004)] IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - An efficient surface potential solution algorithm for compact MOSFET models

Rios, R., Mudanai, S., Wei-Kai Shih,, Packan, P.

Year:

2004

Language:

english

File:

PDF, 232 KB

english, 2004

6

[IEEE 15th Biennial University/Government/Industry Microelectronics Symposium - Boise, ID, USA (30 June-2 July 2003)] Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) - A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO/sub 2//high-K gate stacks

Fei Li,, Mudanai, S.P., Yang-Yu Fan,, Wei Zhao,, Register, L.F., Banerjee, S.K.

Year:

2003

Language:

english

File:

PDF, 240 KB

english, 2003

7

[IEEE Device Research Conference. Conference Digest - Notre Dame, IN, USA (25-27 June 2001)] Device Research Conference. Conference Digest (Cat. No.01TH8561) - A new and accurate quantum mechanical compact model for NMOS gate capacitance

Mudanai, S., Register, L.F., Tasch, A.F., Banerjee, S.K.

Year:

2001

Language:

english

File:

PDF, 164 KB

english, 2001

8

[IEEE 2015 Symposium on VLSI Technology - Kyoto, Japan (2015.6.16-2015.6.18)] 2015 Symposium on VLSI Technology (VLSI Technology) - High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology

Giles, M. D., Arkali Radhakrishna, N., Becher, D., Kornfeld, A., Maurice, K., Mudanai, S., Natarajan, S., Newman, P., Packan, P., Rakshit, T.

Year:

2015

Language:

english

File:

PDF, 208 KB

english, 2015

9

[IEEE 2015 IEEE International Integrated Reliability Workshop (IIRW) - South Lake Tahoe, CA, USA (2015.10.11-2015.10.15)] 2015 IEEE International Integrated Reliability Workshop (IIRW) - Aging model challenges in deeply scaled tri-gate technologies

Ramey, S., Lu, Y., Meric, I., Mudanai, S., Novak, S., Prasad, C., Hicks, J.

Year:

2015

Language:

english

File:

PDF, 1.59 MB

english, 2015

10

An Improved Flicker Noise Model for Circuit Simulations

Roy, Ananda S., Kim, Sungwon, Mudanai, Sivakumar P.

Journal:

IEEE Transactions on Electron Devices

Year:

2017

Language:

english

File:

PDF, 1.12 MB

english, 2017

11

Tinkering with the well-tempered MOSFET: source–channel barrier modulation with high-permittivity dielectrics

D.L. Kencke, Q. Ouyang, W. Chen, H. Wang, S. Mudanai, A. Tasch, S.K. Banerjee

Journal:

Superlattices and Microstructures

Year:

2000

Language:

english

File:

PDF, 406 KB

english, 2000

12

An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers

Chindalore, G.L., McKeon, J.B., Mudanai, S., Hareland, S.A., Shih, W.-K., Wang, C., Tasch, A.F., Jr., Maziar, C.M.

Journal:

IEEE Transactions on Electron Devices

Year:

1998

Language:

english

File:

PDF, 274 KB

english, 1998

13

Temperature dependence characterization of effective electron and hole mobilities in the accumulation layers of n- and p-type MOSFET's

Chindalore, G., Mudanai, S., Shih, W.-K., Tasch, A.F., Jr., Maziar, C.M.

Journal:

IEEE Transactions on Electron Devices

Year:

1999

Language:

english

File:

PDF, 171 KB

english, 1999

14

Models for electron and hole mobilities in MOS accumulation layers

Mudanai, S., Chindalore, G.L., Shih, W.-K., Wang, H., Ouyang, Q., Tasch, A.F., Jr., Maziar, C.M., Banerjee, S.K.

Journal:

IEEE Transactions on Electron Devices

Year:

1999

Language:

english

File:

PDF, 396 KB

english, 1999

15

Modeling of direct tunneling current through gate dielectric stacks

Mudanai, S., Yang-Yu Fan, Qiqing Ouyang, Tasch, A.F., Banerjee, S.K.

Journal:

IEEE Transactions on Electron Devices

Year:

2000

Language:

english

File:

PDF, 182 KB

english, 2000

16

A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current

Qiqing Ouyang, Xiangdong Chen, Mudanai, S.P., Xin Wang, Kencke, D.L., Tasch, A.F., Register, L.F., Banerjee, S.K.

Journal:

IEEE Transactions on Electron Devices

Year:

2000

Language:

english

File:

PDF, 503 KB

english, 2000

17

A physically based compact gate C-V model for ultrathin (EOT ∼1 nm and below) gate dielectric MOS devices

Fei Li, Mudanai, S., Register, L.F., Banerjee, S.K.

Journal:

IEEE Transactions on Electron Devices

Year:

2005

Language:

english

File:

PDF, 592 KB

english, 2005

18

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT ∼ 1 nm) SiO2 and high-κ gate stacks

Fei Li, Mudanai, S.P., Yang-Yu Fan, Register, L.F., Banerjee, S.K.

Journal:

IEEE Transactions on Electron Devices

Year:

2006

Language:

english

File:

PDF, 429 KB

english, 2006

19

Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs

Mudanai, S., Wei-Kai Shih, Rios, R., Xuemei Xi, Jung-Hoon Rhew, Kuhn, K., Packan, P.

Journal:

IEEE Transactions on Electron Devices

Year:

2006

Language:

english

File:

PDF, 353 KB

english, 2006

20

Process Technology Variation

Kuhn, K.J., Giles, M.D., Becher, D., Kolar, P., Kornfeld, A., Kotlyar, R., Ma, S.T., Maheshwari, A., Mudanai, S.

Journal:

IEEE Transactions on Electron Devices

Year:

2011

Language:

english

File:

PDF, 2.14 MB

english, 2011

21

Capacitance Compact Model for Ultrathin Low-Electron-Effective-Mass Materials

Mudanai, S., Roy, A., Kotlyar, R., Rakshit, T., Stettler, M.

Journal:

IEEE Transactions on Electron Devices

Year:

2011

Language:

english

File:

PDF, 207 KB

english, 2011

22

[IEEE 58th DRC. Device Research Conference - Denver, CO, USA (19-21 June 2000)] 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) - Modeling high k gate current from p-type Si inversion layers

Fan, Y.-Y., Mudanai, S., Qi, W., Lee, J.C., Tasch, A.F., Register, L.F., Banerjee, S.K.

Year:

2000

Language:

english

File:

PDF, 180 KB

english, 2000

23

[IEEE 2000 International Conference on Simulation of Semiconductor Processes and Devices - Seattle, WA, USA (6-8 Sept. 2000)] 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) - Modeling of direct tunneling current through gate dielectric stacks

Mudanai, S., Fan, Y.-Y., Ouyang, Q., Tasch, A.F., Register, F., Kwong, D.L., Banerjee, S.

Year:

2000

Language:

english

File:

PDF, 376 KB

english, 2000

24

Understanding the effects of wave function penetration on the inversion layer capacitance of NMOSFETs

Mudanai, S., Register, L.F., Tasch, A.F., Banerjee, S.K.

Journal:

IEEE Electron Device Letters

Year:

2001

Language:

english

File:

PDF, 57 KB

english, 2001

25

[IEEE 1999 57th Annual Device Research Conference Digest - Santa Barbara, CA, USA (28-30 June 1999)] 1999 57th Annual Device Research Conference Digest (Cat. No.99TH8393) - Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs

Kencke, D.L., Chen, W., Wang, H., Mudanai, S., Ouyang, Q., Tasch, A., Banerjee, S.K.

Year:

1999

Language:

english

File:

PDF, 221 KB

english, 1999

26

[IEEE 2000 International Conference on Simulation of Semiconductor Processes and Devices - Seattle, WA, USA (6-8 Sept. 2000)] 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) - Two-dimensional bandgap engineering in a novel Si-SiGe pMOSFET with enhanced device performance and scalability

Ouyang, Q., Chen, X.D., Mudanai, S., Kencke, D.L., Wang, X., Tasch, A.F., Register, L.F., Banerjee, S.K.

Year:

2000

Language:

english

File:

PDF, 295 KB

english, 2000

27

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

Mudanai, S., Li, F., Samavedam, S.B., Tobin, P.J., Kang, C.S., Nieh, R., Lee, J.C., Register, L.F., Banerjee, S.K.

Journal:

IEEE Electron Device Letters

Year:

2002

Language:

english

File:

PDF, 252 KB

english, 2002

28

[IEEE IEEE International Electron Devices Meeting - San Francisco, CA, USA (8-11 Dec. 2002)] Digest. International Electron Devices Meeting, - A three-transistor threshold voltage model for halo processes

Rios, R., Wei-Kai Shih,, Shah, A., Mudanai, S., Packan, P., Sandford, T., Mistry, K.

Year:

2002

Language:

english

File:

PDF, 227 KB

english, 2002

29

[IEEE 2010 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2010.12.6-2010.12.8)] 2010 International Electron Devices Meeting - RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Jan, C.-H., Agostinelli, M., Deshpande, H., El-Tanani, M. A., Hafez, W., Jalan, U., Janbay, L., Kang, M., Lakdawala, H., Lin, J., Lu, Y-L, Mudanai, S., Park, J., Rahman, A., Rizk, J., Shin, W.-K., Sou

Year:

2010

Language:

english

File:

PDF, 1.10 MB

english, 2010

30

Compact Model for Ultrathin Low Electron Effective Mass Double Gate MOSFET

Roy, Ananda S., Mudanai, Sivakumar P., Basu, Dipanjan, Stettler, Mark A.

Journal:

IEEE Transactions on Electron Devices

Year:

2014

Language:

english

File:

PDF, 1.29 MB

english, 2014

31

Compressive Uniaxial Stress Bandstructure Engineering for Transferred-Hole Devices

Kotlyar, Roza, Giles, Martin D, Mudanai, Sivakumar P, Kuhn, Kelin J, Cea, Stephen M, Linton, Thomas D, Pillarisetty, Ravi

Journal:

IEEE Electron Device Letters

Year:

2010

Language:

english

File:

PDF, 449 KB

english, 2010

32

[IEEE 61st Device Research Conference - Salt Lake City, UT, USA (23-25 June 2003)] 61st Device Research Conference. Conference Digest (Cat. No.03TH8663) - Compact model of MOSFET electron tunneling current through ultra-thin SiO/sub 2/ and high-k gate stacks

Fei Li,, Mudanai, S.P., Yang-Yu Fan,, Register, L.F., Banerjee, S.K.

Year:

2003

Language:

english

File:

PDF, 201 KB

english, 2003

33

[IEEE IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - San Francisco, CA, USA (Dec. 13-15, 2004)] IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - Predictive compact modeling of HQS effects and thermal noise in 90nm mixed signal/RF CMOS technology

Wei-Kai Shih,, Mudanai, S., Rios, R., Packan, P., Becher, D., Basco, R., Celia Hung,, Jalan, U.

Year:

2004

Language:

english

File:

PDF, 265 KB

english, 2004

34

[IEEE 56th Annual Device Research Conference Digest - Charlottesville, VA, USA (22-24 June 1998)] 56th Annual Device Research Conference Digest (Cat. No.98TH8373) - Temperature characterization and modeling of electron and hole mobilities in MOS accumulation layers

Mudanai, S., Chindalore, G., Shih, W.-K., Wang, H., Tasch, A.F., Maziar, C.M.

Year:

1998

File:

PDF, 317 KB

1998

35

[IEEE 58th DRC. Device Research Conference - Denver, CO, USA (19-21 June 2000)] 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) - Bandgap engineering in deep submicron vertical pMOSFETs

Ouyang, Q., Chen, X.D., Mudanai, S., Kencke, D.L., Tasch, A.F., Banerjee, S.K.

Year:

2000

Language:

english

File:

PDF, 175 KB

english, 2000

36

[IEEE International Electron Devices Meeting. Technical Digest. IEDM - San Francisco, CA, USA (10-13 Dec. 2000)] International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - Enhanced secondary electron injection in novel SiGe flash memory devices

Kencke, D.L., Xin Wang,, Ouyang, Q., Mudanai, S., Tasch, A., Banerjee, S.K.

Year:

2000

Language:

english

File:

PDF, 319 KB

english, 2000

37

Compact Modeling of Magnetic Tunneling Junctions

Roy, Ananda S., Sarkar, Angik, Mudanai, Sivakumar P.

Journal:

IEEE Transactions on Electron Devices

Year:

2016

Language:

english

File:

PDF, 1.51 MB

english, 2016

38

[IEEE 2017 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2017.12.2-2017.12.6)] 2017 IEEE International Electron Devices Meeting (IEDM) - 22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications

Sell, B., Bigwood, B., Cha, S., Chen, Z., Dhage, P., Fan, P., Giraud-Carrier, M., Kar, A., Karl, E., Ku, C.-J., Kumar, R., Lajoie, T., Lee, H.-J., Liu, G., Liu, S., Ma, Y., Mudanai, S., Nguyen, L., Pa

Year:

2017

File:

PDF, 621 KB

2017

39

[IEEE 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Kamakura, Japan (2017.9.7-2017.9.9)] 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Unique challenges in compact modeling

Mudanai, S., Roy, A. S.

Year:

2017

Language:

english

File:

PDF, 304 KB

english, 2017

40

From Process Corners to Statistical Circuit Design Methodology: Opportunities and Challenges

Dongaonkar, Sourabh, Mudanai, Sivakumar P., Giles, Martin D.

Journal:

IEEE Transactions on Electron Devices

Year:

2018

Language:

english

File:

PDF, 2.21 MB

english, 2018

41

[IEEE 2019 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2019.12.7-2019.12.11)] 2019 IEEE International Electron Devices Meeting (IEDM) - Role of correlation in systematic variation modeling

Roy, Ananda S., Dongaonkar, Sourabh, Mudanai, Sivakumar P.

Year:

2019

File:

PDF, 2.99 MB

2019